參數(shù)資料
型號(hào): TLV320AIC29_07
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: STWREO AUDIO CODEC WITH INTERGRATED HEADPHONE AND SPEAKER AMPLIFIERS
中文描述: STWREO音頻編解碼器集成耳機(jī)和音箱放大器
文件頁數(shù): 11/94頁
文件大?。?/td> 1073K
代理商: TLV320AIC29_07
TLV320AIC29
SLAS494A DECEMBER 2005 REVISED JANUARY 2006
www.ti.com
19
OVERVIEW
The AIC29 is a highly integrated stereo audio DAC and mono audio ADC for portable computing,
communication and entertainment applications. The AIC29 has a register-based architecture where all
peripheral functions are controlled through the registers and on-board state machines.
The AIC29 consists of the following blocks:
D Audio Codec
D Headset and Button Detection
D Battery Monitors
D Auxiliary Inputs
D Temperature Monitor
Communication to the AIC29 is via a standard SPI serial interface. This interface requires that the Slave Select
signal (SS) be driven low to communicate with the AIC29. Data is then shifted into or out of the AIC29 under
control of the host microprocessor, which also provides the serial data clock.
Control of the AIC29 and its functions is accomplished by writing to different registers in the AIC29. A simple
command protocol is used to address the 16-bit registers. Registers control the operation of the SAR ADC and
audio codec.
OPERATION—AUDIO CODEC
AUDIO ANALOG I/O
The AIC29 has stereo audio DAC and mono audio ADC. It has a wide range of analog interfaces to support
different headsets and analog outputs. The AIC29 has features to interface output drivers (8-
, 16-, 32-)
and Microphone PGA to Cell-phone. The AIC29 also has a virtual ground (VGND) output, which can be
optionally used to connect to the ground terminal of a speaker of headphone to eliminate the ac-coupling
capacitor needed at the speaker or headphone output. A special circuit has also been included in the AIC29
to insert a short keyclick sound into the stereo audio output, even when the audio DAC is powered down. They
keyclick sound is used to provide feedback to the used when a particular button is pressed or item is selected.
The specific sound of the keyclick can be adjusted by varying several register bits that control its frequency,
duration, and amplitude.
AUDIO DIGITAL I/O INTERFACE
Digital audio data samples can be transmitted between the AIC29 and the CPU via the serial bus (BCLK, WCLK,
SDOUT, SDIN) that can be configured to transfer digital data in four different formats: Right justified (RJF), Left
justified (LJF), I2S and DSP. The four modes are MSB first and operate with variable word length between
16/20/24/32 bits. The AIC29’s audio codec can operate in master or slave mode, depending on the setting of
D11 at the register 06h of page 2. The word-select signal (WCLK) and bit clock signal (BCLK) are configured
as inputs when the bus is in slave mode (D11 = 0). They are configured as outputs when the bus is in master
mode (D11 = 1). Under master mode, both clocks start running when the I2S bus needs to be active (one of
the analog input/output paths has been configured and powered up). The WCLK is representative of the
sampling rate of the audio ADC/DAC and is synchronized with SDOUT. Although the SDOUT signal can contain
two channels of information (a left and right channel), the AIC29 sends the same ADC data in both channels.
D ADC/DAC Sampling Rate
The audio-control-1 register (Register 00H, Page 2) determines the sampling rates of DAC and ADC. The
sampling frequency is scaled down from the reference rate (Fsref). The reference rate is usually either 44.1
kHz or 48 kHz which can be selectable using bit D13 of the register Audio Control 3 (06H/Page2). The ADC
and DAC can operate with either common WCLK (equal sampling rates) or separate GPIO1 (For ADC) and
WCLK (For DAC) for unequal sampling rates. When the audio codec is powered up, it is by default configured
as an I2S slave with both the DAC and ADC operating at Fsref.
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