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參數(shù)資料
| 型號： | TLV320AIC24KIPFBRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 17/52頁 |
| 文件大小： | 981K |
| 代理商： | TLV320AIC24KIPFBRG4 |
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IIR/FIR Control
Overflow Flags
IIR/FIR Bypass Mode
System Reset and Power Management
Software and Hardware Reset
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Description (continued)
The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input analog
signal has exceeded the range of internal decimation filter calculations. The interpolation IIR/FIR filter sets an
overflow flag (bit D4) of control register 1 indicating that the digital input has exceeded the range of internal
interpolation filter calculations. When the IIR/FIR overflow flag is set in the register, it remains set until the user
reads the register. Reading this value resets the overflow flag. These flags need to be reset after power up by
reading the register. If FIR/IIR overflow occurs, the input signal should be attenuated by either the PGA or some
other method.
An option is provided to bypass IIR/FIR filter sections of the decimation filter and the interpolation filter. This
mode is selected through bit D6 of control register 2 and effectively increases the frequency of the FS signal to
four times normal output rate of the IIR/FIR-filter. For example, for a normal sampling rate of 8 Ksps (i.e., FS = 8
kHz) with IIR/FIR, if the IIR/FIR is bypassed, the frequency of FS is readjusted to 4×8 kHz = 32 kHz. The sync
filters of the two paths can not be bypassed. A maximum of four devices in cascade can be supported in the
IIR/FIR bypass mode.
In this mode , the ADC channel outputs data which has been decimated only till 4 FS. Similarly DAC channel
input needs to be preinterpolated to 4 FS before being given to the device. This mode allows users the flexibility
to implement their own filter in DSP for decimation and interpolation. M should be a multiple of 4 during IIR/FIR
bypass mode.
The TLV320AIC2x resets internal counters and registers in response to either of two events:
A low-going reset pulse is applied to terminal RESET
A 1 is written to the programmable software reset bits (D3 of control register 3A)
NOTE: The TLV320AIC2x requires a power-up reset applied to the RESET pin.
Either event resets the control registers and clears all sequential circuits in the device. The H/W RESET (active
low) signal is at least 6 master clock periods long. As soon as the RESET input is applied, the TLV320AIC2x
enters the initialization cycle that lasts for 132 MCLKs, during which the serial port of the DSP must be 3-stated.
The initialization sequence performed by the AIC2x is known as Auto Cascade Detection (ACD). ACD is a
mechanism that allows a device to know its address in a cascade chain. Up to 8 AIC2x devices can be cascaded
together.
The Master device is the first device on the chain i.e. the FS of the Master is connected to the FS of the DSP.
During ACD, each device gets to know the number of devices in the chain as well as its relative position in the
chain. This is done upon hardware reset. Therefore. after power up, a hardware reset must be completed. ACD
requires 132 MCLKs after reset to complete operation. The number of MCLKs is independent of the number of
devices in the chain.
Adjacent devices in the chain have their FS and FSD pins connected to each other. The master device’s FS is
connected to the FS pin of the DSP. The FSD pin on the last device in the chain is pulled high for master-slave
configuration, and it is pulled low for stand-alone slave configuration.
The master device has the highest address i.e., the master device has address equal to total no of channels in
cascade minus 1. For example, if 8 devices are cascaded, then the master device has address 15 and 14
followed by the next device which has 13 and 12 etc.
During the first 64 MCLKs, FS is configured as an output and FSD as an input.
During the next 64 MCLKs, FS is configured as an input and FSD as an output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320AIC25 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PRODUCT NOTIFICATION |
| TLV320AIC25C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Layout and Grounding Guidelines for TLV320AIC2x |
| TLV320AIC25CPFB | 功能描述:接口—CODEC Low Power Low IOVdd Dual Channel RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC25CPFBG4 | 功能描述:接口—CODEC 512 x 18 3.3-V Synch FIFO Memory RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC25CPFBR | 功能描述:接口—CODEC Low Power Low IOVdd Dual Channel RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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