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參數(shù)資料
| 型號： | TLV320AIC24KIPFBRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 981K |
| 代理商： | TLV320AIC24KIPFBRG4 |
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Internal Architecture
Analog Low Pass Filter
Sigma-Delta ADC
Decimation Filter
Sigma-Delta DAC
Interpolation Filter
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Description (continued)
7. Both equations of FS require that the following conditions should be met
–
(M x N x P)
≤ (devnum mode) if the FIR/IIR filter is not bypassed.
–
[Integer(M/4) x N x P]
≥ (devnum mode) if the FIR/IIR filter is bypassed.
Where:
devnum is the number of codec channels connecting in cascade (devnum = 2 for
standalone AIC20) mode is equal to 1 for continuous data transfer mode and 2 for
programming mode.
8. If the DAC OSR is set to 512, then M needs to be a multiple of 4. If the DAC OSR
is set to 256, then M needs to be a multiple of 2. M can take any value between 1
and 128 if the OSR is set to 128.
Example:
The MCLK comes from the DSP C5402 CLKOUT and equals to 20.48 MHz and the
conversion rate of 8 kHz is desired. First, set P = 1 to satisfy condition 5 so that
(MCLK/P) = 20.48 MHz/1 = 20.48 MHz. Next, pick M = 10 and N = 16 to satisfy
condition 65 and derive 8 kHz for FS. That is, FS = 20.48 MHz/ (16 x 10 x 16 x 1) = 8
kHz.
The built-in analog low pass antialiasing filter is a two-pole filter that has a 20-dB attenuation at 1 MHz.
The sigma-delta analog-to-digital converter is a sigma-delta modulator with 128x oversampling. The ADC
provides high-resolution, low-noise performance using oversampling techniques.
The decimation filters consist of a sinc filter stage followed by either FIR filters or IIR filters selected by bit D5 of
the control register 1. The FIR filter provides linear-phase output with 17/fs group delay, whereas the IIR filter
generates nonlinear phase output with negligible group delay. The decimation filters reduce the digital data rate
to the sampling rate. This is accomplished by decimating with a ratio of 1:128. The output of the decimation filter
is a 16-bit 2s-complement data word clocking at the sample rate selected for that particular data channel. The
BW of the filter is (0.45 × FS) and scales linearly with the sample rate.
The sigma-delta digital-to-analog converter is a sigma-delta modulator with 128x oversampling. The DAC
provides high-resolution, low-noise performance using oversampling techniques. The oversampling ratio (OSR)
in DAC is programmable to 256/512 using bits D0-D1 of register 3C, the default being 128. The OSR of 512 is
recommended when the FS is a maximum of 8 Ksps, and an OSR of 256 is recommended when the FS is a
maximum of 16 Ksps. It is also required that the value of M used in programming the PLL be a multiple of 4 if the
OSR is set to 512 and 2 if the OSR is set to 256
The interpolation filters consist of either FIR or IIR filters selected by bit D5 of control register 1 followed by a sinc
filter stage. The FIR filter provides linear-phase output with 18/fs group delay, whereas the IIR filter generates
nonlinear phase output with negligible group delay. The interpolation filter resamples the digital data at a rate of
128 times the incoming sample rate. The high-speed data output from the interpolation filter is then used in the
sigma-delta DAC. The BW of the filter is (0.45 × FS) and scales linearly with the sample rate.
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