參數(shù)資料
型號(hào): TLV320AIC10C
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: General-Purpose 3V to 5.5V 16-bit 22-KSPS DSP CODEC
中文描述: 通用3V至5.5V 16位22 kSPS的DSP的解碼器
文件頁(yè)數(shù): 51/57頁(yè)
文件大小: 284K
代理商: TLV320AIC10C
A–1
Appendix A
Register Set
Bits D15 through D13 represent the device address in the cascade set by the automatic cascade detection described
in Section 2.1.13. In cascading, the master is the device directly connected to the DSP. For example, if there are four
devices in the cascade, as shown in row 4 of Table A-1 and in Section 2.7.5, the device address D15-D13 of the master
will have a binary value of 011 The other three slaves’ addresses are 010 001,and 000,corresponding to their
positions in the cascade. The device address for a stand-alone device is always 000 Bits D11 through D8 comprise
the address of the register that is written with data carried in D7 through D0. D12 determines a read or write cycle
to the addressed register; a low selects a write cycle.
The following table shows the register map.
REGISTER MAP
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Device Address
RW
Register Address
X
Control Register Content
Table A–1. Device Address
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
Device Address R/W Register Adress
X
Register Content
Device 0
000
000
REGISTER MAP
000
000
000
000
000
000
Device 1
001
001
001
001
001
001
001
Device 2
010
010
010
010
010
010
Device 3
011
011
011
011
011
Device 4
100
100
100
100
Device 5
101
101
101
Device 6
110
110
Device 7
111
8
7
6
5
4
3
1
2
DEVICE ADDRESS (D15–D13)
# Devices
in Cascade
Table A–2. Register Address
REGISTER NO.
D11
D10
D9
REGISTER NAME
0
0
0
0
No operation
1
0
0
1
Control 1
2
0
1
0
Control 2
3
0
1
1
Control 3
4
1
0
0
Control 4
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