參數(shù)資料
型號(hào)： TLV320AIC10C
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： General-Purpose 3V to 5.5V 16-bit 22-KSPS DSP CODEC
中文描述： 通用3V至5.5V 16位22 kSPS的DSP的解碼器
文件頁(yè)數(shù)： 25/57頁(yè)
文件大小： 284K
代理商： TLV320AIC10C
2–11
2.7.3
Frame-Sync (FS) Function—Master Mode
The master mode in the TLV320AIC10 is selected by connecting pin M/S pin to HI. In the master mode, the
TLV320AIC10 generates the frame-sync signal (FS) to the DSP that goes low on the rising edge of SCLK and remains
low during a 16-bit data transfer.
DIN/DOUT
Primary
Secondary
16 SCLKs
Primary
16 SCLKs
FS
(see Note B)
FS
(see Note A)
Primary
Secondary
Primary
NOTES: A. Primary and secondary serial communications
B. Primary serial communication only
Figure 2–13. Master Device Frame-Sync Signal With Primary and Secondary Communication ( No Slaves)
2.7.4
Frame-Sync (FS) Function—Slave Mode
The slave mode is selected by connecting pin M/S to LO. The frame-sync timing is generated externally by the master,
as shown in Figure 2–14 (that is, FSD) and is applied to FS of the slave to control the ADC and DAC timing.
MP
32 SCLKs
FSD (Master)
to FS (Slave)
FS
(Master to DSP)
SP
MS
SS
MP
NOTE: MP: master primary (master-device data is transferred during this period, the DOUT of the slave device is in high-impedance state).
SP: slave primary (slave device data is transferred during this period, the DOUT of master device is in high-impedance state).
MS: master secondary (master device control register information is transferred during this period, the DOUT of slave device is in high-
impedance state).
SS: slave secondary (slave device control register information is transferred during this period, the DOUT of master device is in high-
impedance state).
Figure 2–14. Master Device’s FS Output to DSP and FSD Output to the Slave
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