參數(shù)資料
型號(hào): TLV2324Y
廠商: Texas Instruments, Inc.
英文描述: Inductive DC
中文描述: LinCMOSE低壓低功耗運(yùn)算放大器
文件頁(yè)數(shù): 26/33頁(yè)
文件大?。?/td> 502K
代理商: TLV2324Y
TLV2322, TLV2322Y, TLV2324, TLV2324Y
LinCMOS
LOW-VOLTAGE LOW-POWER
OPERATIONAL AMPLIFIERS
SLOS187 – FEBRUARY 1997
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
input characteristics (continued)
+
+
+
(a) NONINVERTING AMPLIFIER
(b) INVERTING AMPLIFIER
(c) UNITY-GAIN AMPLIFIER
Vi
VI
VI
VO
VO
VO
Figure 42. Guard-Ring Schemes
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias-current requirements of the TLV232x result in a very low noise current,
which is insignificant in most applications. This feature makes the device especially favorable over bipolar
devices when using values of circuit impedance greater than 50 k
, since bipolar devices exhibit greater noise
currents.
feedback
Operational amplifier circuits nearly always
employ feedback, and since feedback is the first
prerequisite for oscillation, caution is appropriate.
Most oscillation problems result from driving
capacitive loads and ignoring stray input
capacitance. A small-value capacitor connected
in parallel with the feedback resistor is an effective
remedy (see Figure 43). The value of this
capacitor is optimized empirically.
electrostatic-discharge protection
The
electrostatic-discharge (ESD)-protection circuit
that prevents functional failures at voltages up to 2000 V as tested under MIL-PRF-38535, Method 3015.2. Care
should be exercised, however, when handling these devices as exposure to ESD can result in the degradation
of the device parametric performance. The protection circuit also causes the input bias currents to be
temperature dependent and have the characteristics of a reverse-biased diode.
TLV232x
incorporates
an
internal
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLV232x inputs
and outputs are designed to withstand –100-mA surge currents without sustaining latch-up; however,
techniques should be used to reduce the chance of latch-up whenever possible. Internal-protection diodes
should not by design be forward biased. Applied input and output voltage should not exceed the supply voltage
+
Figure 43. Compensation for Input Capacitance
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