參數(shù)資料
型號(hào): TLV1571EVM
廠商: Texas Instruments, Inc.
英文描述: TLV1571 Evaluation Module(TLV1571評(píng)估板)
中文描述: TLV1571評(píng)估模塊(TLV1571評(píng)估板)
文件頁數(shù): 46/50頁
文件大?。?/td> 1324K
代理商: TLV1571EVM
Programming Model
4-2
4.1
Programming Model
The EVM uses an MSB model. The illustration below indicates how bits from
a host system are mapped to the corresponding bits on the EVM.
To maintain software compatibility between each device in the family, it is
important to note that bits D0 and D1 of the TLV571 EVM are grounded, and
cannot be used. Since these bits control the MUX channel selected and some
self-test results, the effect of their loss from the TLV571
s functionality is small.
Table 4
1.Data Bus Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TLV1578
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
TLV1571
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
TLV571
D07
D06
D05
D04
D03
D02
D01
D00
4.2
Control Register 0
CR0
Table 4
2.Control Register 0 (Read/Write)
7
6
5
4
3
2
1
0
STARTSEL
PROG EOC
CLKSEL
SWPWDN
MODESEL
CHSEL (2-0)
Bit 7 STARTSEL
STARTSEL determines hardware- or software-start for data conversion.
STARTSEL
0
Hardware conversion mode selected
1
Software conversion mode selected
Bit 6 PROGEOC
PROGEOC determines how the ADC signals the host that a conversion has
taken place.
0
An interrupt signal, INT, is generated after each conversion.
PROGEOC
1
An EOC signal is deasserted at the beginning of the
conversion, and asserted at the end of the conversion.
The INT/EOC signal is available through pin 17 of connector J7.
Bit 5 CLKSEL
CLKSEL establishes which clock signal is used by the ADC.
CLKSEL
0
Internal clock selected
The TLV1578 has an integrated oscillator. Its value can be set
to 10
±
1 MHz or 20
±
2 MHz by CR1.6.
1
External clock selected
The external clock input is available via J10 pin33.
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