參數(shù)資料
型號: TLV1570EVM
廠商: Texas Instruments, Inc.
英文描述: TLV1570 Evaluation Module(TLV1570評估板)
中文描述: TLV1570評估模塊(TLV1570評估板)
文件頁數(shù): 18/34頁
文件大小: 226K
代理商: TLV1570EVM
Digital Interface
3-2
Digital Interface
3.1
Digital Interface
The digital interface consists of six signals that are accessible through J2:
Serial clock (SCLK)
Data in (DIN)
Data out (DOUT)
Frame synchronization (FS)
Chip-select ADC (/CSAD)
Chip-select DAC (/CSDA)
The pin assignments of J2 (see Table 3–1) are compatible with the WYLE TI
C2xx Development System, featuring a TMS320C203 DSP. J2 can be
connected directly to JP3 on the WYLE board. /CSAD is then connected to IO0
of the TMS320C203 and /CSDA to IO1. The positive power supply must be
hardwired to pin 26, as the WYLE board does not provide a signal on pin 26
of JP3 (not used).
Both converters [TLV1570 and the onboard DAC (TLV5616)] have a
TMS320-compatible serial-interface timing. The active device is determined
by two chip-select signals; /CSAD for the TLV1570 and /CSDA for the
TLV5616. Usually, one chip-select signal always should be high to ensure
proper signal routing. However, no bus conflict occurs if both signals are low
(not recommended).
Table 3–1.J2 Pin Assignments
Pin No.
Name
Pin No.
Name
1
NC
2
NC
3
NC
4
NC
5
NC
6
NC
7
NC
8
NC
9
NC
10
NC
11
NC
12
NC
13
/CSAD
14
/CSDA
15
NC
16
NC
17
CLKOUT
18
NC
19
DIN
20
FS
21
CLKIN
22
DOUT
23
FS
24
CLKIN
25
GND
26
3V–5V
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