- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383955 > TLK1101ERGPT (Texas Instruments, Inc.) 11.3-Gbps Cable and PC Board Equalizer PDF資料下載
參數(shù)資料
| 型號(hào)： | TLK1101ERGPT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 11.3-Gbps Cable and PC Board Equalizer |
| 中文描述： | 11.3 - Gbps的電纜和PC板均衡 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 1564K |
| 代理商： | TLK1101ERGPT |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
www.ti.com
TWO-WIRE SERIAL INTERFACE AND CONTROL LOGIC
FUNCTIONAL DESCRIPTION
The TLK1101E uses a two-wire serial interface for digital control. The two circuit inputs, SDA and SCL, are
driven, respectively, by the serial data and serial clock from a microcontroller, for example. Both inputs include
100k
pull-up resistors to VCC. For driving these inputs, an open-drain output is recommended.
t
BUF
t
HDSTA
t
r
t
LOW
t
HDDAT
t
HIGH
t
f
t
SUDAT
t
SUSTA
t
HDSTA
t
SUSTO
P
S
S
P
SDA
SCL
TLK1101E
SLLS845A–AUGUST 2007–REVISED OCTOBER 2007
The two-wire interface allows write access to the internal memory map to modify control registers and read
access to read out control and status signals. The TLK1101E is a slave device only which means that it cannot
initiate a transmission itself; it always relies on the availability of the SCL signal for the duration of the
transmission. The master device provides the clock signal as well as the START and STOP commands. The
protocol for a data transmission is as follows:
1. START command
2. 7-bit slave address (0101000) followed by an eighth bit which is the data direction bit (R/W). A zero indicates
a WRITE and a 1 indicates a READ.
3. 8-bit register address
4. 8-bit register data
5. STOP command
Regarding timing, the TLK1101E is I
2
C-compatible. The typical timing is shown in
Figure 4
and a complete data
transfer is shown in
Figure 5
. Parameters for
Figure 4
are defined in
Table 3
.
Bus Idle:
Both SDA and SCL lines remain HIGH
Start Data Transfer
: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH,
defines a START condition (S). Each data transfer is initiated with a START condition.
Stop Data Transfer:
A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH
defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still
wishes to communicate on the bus, it can generate a repeated START condition and address another slave
without first generating a STOP condition.
Data Transfer:
The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge:
Each receiving device, when addressed, is obliged to generate an acknowledge bit. The
transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the
acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver does not
acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a
STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time
later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by
the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the
master generates the STOP condition.
Figure 4. Two-Wire Serial Interface Timing Diagram.
Copyright 2007, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s):
TLK1101E
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLK1221RHA | ETHERNET TRANSCEIVER |
| TLP630 | Programmable Controllers AC / DC−Input Module Telecommunication |
| TLV0832(中文) | 3-VOLT 8-Bit ADC With Serial Control(3V，單通道，帶串行控制，8位ADC) |
| TLV0831(中文) | 3-VOLT 8-Bit ADC With Serial Control(3V，單通道，帶串行控制，8位ADC) |
| TLV0834(中文) | 3-VOLT 8-Bit ADC With Serial Control(3V，4通道，帶串行控制，8位ADC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLK1101ERGPTG4 | 功能描述:光纖發(fā)射器、接收器、收發(fā)器 11.3Gb/s Cable & PC Board Equalizer RoHS:否 制造商:Omron Electronics 產(chǎn)品:Transmitters 數(shù)據(jù)速率:3.5 Gbps 波長:850 nm 最大工作溫度: 最小工作溫度: 封裝 / 箱體: 封裝: |
| TLK1102E | 制造商:TI 制造商全稱:Texas Instruments 功能描述:11.3-Gbps Dual-Channel Cable and PC Board Equalizer |
| TLK1102E_10 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:11.3-Gbps Dual-Channel Cable and PC Board Equalizer |
| TLK1102ERGER | 功能描述:接口 - 專用 11.3Gbps 2Ch Cable & PC Brd Equalizer RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| TLK1102ERGET | 功能描述:光纖發(fā)射器、接收器、收發(fā)器 11.3Gbps 2Ch Cable & PC Brd Equalizer RoHS:否 制造商:Omron Electronics 產(chǎn)品:Transmitters 數(shù)據(jù)速率:3.5 Gbps 波長:850 nm 最大工作溫度: 最小工作溫度: 封裝 / 箱體: 封裝: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。