參數(shù)資料
型號: TLK1101ERGPT
廠商: Texas Instruments, Inc.
英文描述: 11.3-Gbps Cable and PC Board Equalizer
中文描述: 11.3 - Gbps的電纜和PC板均衡
文件頁數(shù): 5/28頁
文件大小: 1564K
代理商: TLK1101ERGPT
www.ti.com
TLK1101E
SLLS845A–AUGUST 2007–REVISED OCTOBER 2007
AC ELECTRICAL CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3V and T
A
= 25
°
C. Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIS = Low, SWG = Low, V
= 400mV
p-p
,
No de-emphasis, No interconnect line
V
CC
–0.113
V
CC
–0.075
V
CC
–0.056
DIS = Low, SWG = Open, V
= 400mV
p-p
,
No de-emphasis, No interconnect line
V
CM,OUT
Data output common-mode voltage
V
CC
–0.2
V
CC
–0.15
V
CC
–0.113
V
DIS = Low, SWG = High, V
= 400mV
p-p
,
No de-emphasis, No interconnect line
V
CC
–0.3
V
CC
–0.225
V
CC
–0.15
DIS = High, 50% Transitions of K28.5 pattern at
11.3Gbps, No interconnect line, V
IN
= 1600mV
p-p
K28.5 Pattern at 11.3Gbps, No interconnect line,
V
= 400mV
, SWG = Open, Output de-emphasis off:
DE0 = Low, DE1 = Low
V
RIP
Differential output ripple
1.5
5
mV
RMS
0
DE
Output de-emphasis
(2)
dB
K28.5 Pattern at 11.3Gbps, No interconnect line,
V
= 400mV
, SWG = Open, Maximum output
de-emphasis: DE0 = High, DE1 = High
7
K28.5 Pattern at 11.3Gbps, 10-m 28-AWG Cable,
V
= 400mV
, SWG = Open, No de-emphasis,
Maximum interconnect length setting
12
DJ
Deterministic jitter
ps
p-p
K28.5 Pattern at 11.3Gbps, 15-m 24-AWG Cable,
V
= 400mV
, SWG = Open, No de-emphasis,
Maximum interconnect length setting
12
K28.5 Pattern at 11.3Gbps, 10-m 28-AWG Cable,
V
= 400mV
, SWG = Open, No de-emphasis,
Maximum interconnect length setting
1.0
RJ
Random jitter
ps
RMS
K28.5 Pattern at 11.3Gbps, 15-m 24-AWG Cable,
V
= 400mV
, SWG = Open, No de-emphasis,
Maximum interconnect length setting
1.0
20% to 80%, No interconnect line,
V
IN
= 400mV
p-p
, SWG = Open, No de-emphasis
20% to 80%, No interconnect line,
V
IN
= 400mV
p-p
, SWG = Open, No de-emphasis
0.01GHz < f < 3.9GHz
t
R
Output rise time
20
28
ps
t
F
Output fall time
20
28
16
SDD11
Differential input return loss
dB
3.9GHz < f < 12.1GHz
See
(3)
0.01GHz < f < 3.9GHz
16
SDD22
Differential output return loss
dB
3.9GHz < f < 12.1GHz
See
(3)
0.01GHz < f < 7.5GHz
25
Input differential to common-mode
conversion
SCD11
dB
7.5GHz < f < 12.1GHz
20
0.01GHz < f < 2.5GHz
13
SCC22
Common-mode output return loss
dB
2.5GHz < f < 12.1GHz
7
K28.5 Pattern at 11.3Gbps, No interconnect,
LOSR = High, LOSL = Open
25
60
V
AS
LOS Assert threshold voltage
mV
p-p
K28.5 Pattern at 11.3Gbps, No interconnect,
LOSR = High, LOSL = 1.0V
75
180
K28.5 Pattern at 11.3Gbps, No interconnect,
LOSR = High, LOSL = Open
100
150
V
DAS
LOS De-assert threshold voltage
mV
p-p
K28.5 Pattern at 11.3Gbps, No interconnect,
LOSR = High, LOSL = 1.0V
300
450
LOS Hysteresis
20log(V
DAS
/ V
AS
)
2.5
4.5
dB
T
AS/DAS
T
DIS
LOS Assert/de-assert time
2.5
50
μ
s
ns
Disable response time
20
Latency
From DIN+/DIN– to DOUT+/DOUT–
150
ps
(2)
(3)
See
Table 1
and
Figure 3
for output de-emphasis settings
Differential Return Loss given by SDD11, SDD22 = 19.3 + 26.66 log
10
(f/8.25), f in GHz
Copyright 2007, Texas Instruments Incorporated
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