參數(shù)資料
型號： TLE7824G
廠商： INFINEON TECHNOLOGIES AG
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： GREEN, PLASTIC,SOP-28
文件頁數(shù)： 38/53頁
文件大小： 900K
代理商： TLE7824G
Data Sheet
43
Rev. 3.01, 2008-04-15
TLE7824G
General Product Characteristics
16.4.103 TxD dominant time out
recovery time
t
torec
–10
–
μs
V
TxD = 5 V
Transfer Rate 20 kbit/s; 1
μs < τ = R
L × Cbus < 5 μs
16.4.104 Duty cycle D1
D1
0.396
–
μs
duty cycle 1:
THRec(max) = 0.744 × VS;
THDom(max) = 0.581 × VS;
V
S = 7.0 … 18 V;
t
bit = 50 μs;
D1 =
t
bus_rec(min) / 2 tbit;
(LIN Spec 2.0;
Line 3.3.1)
16.4.105 Duty cycle D2
D2
–
0.581
μs
duty cycle 2:
THRec(min) = 0.422 × VS;
THDom(min) = 0.284 × VS;
V
S = 7.6 … 18 V;
t
bit = 50 μs;
D2 =
t
bus_rec(max) / 2 tbit;
(LIN Spec 2.0;
Line 3.3.2)
Transfer Rate 10.4 kbit/s; 1
μs < τ = R
L × Cbus < 5 μs
16.4.106 Duty cycle D3
D3
0.417
–
μs
duty cycle 3:
THRec(max) = 0.778 × VS;
THDom(max) = 0.616 × VS;
V
S = 7.0 … 18 V;
t
bit = 96 μs;
D3 =
t
bus_rec(min) / 2 tbit;
(LIN Spec 2.0;
Line 3.4.1)
16.4.107 Duty cycle D4
D4
–
0.590
μs
duty cycle 4:
THRec(min) = 0.389 × VS;
THDom(min) = 0.251 × VS;
V
S = 7.6 … 18 V;
t
bit = 96 μs;
D4 =
t
bus_rec(max) / 2 tbit;
(LIN Spec 2.0;
Line 3.4.2)
SPI Data Input Timing1)
16.4.108 Clock period
t
pCLK
250
–
ns
–
16.4.109 Clock high time
t
CLKH
125
–
ns
–
16.4.110 Clock low time
t
CLKL
125
–
ns
–
16.4.111 Clock low before CSN low
t
bef
125
–
ns
–
16.4.112 CSN setup time
t
lead
250
–
ns
–
16.4.113 CLK setup time
t
lag
250
–
ns
–
Table 14
Electrical Characteristics (cont’d)
V
S = 13.5 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
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