參數(shù)資料
型號(hào)： TLE6288R
廠商： INFINEON TECHNOLOGIES AG
英文描述： Smart 6 Channel Peak&Hold Switch
中文描述： 智能6通道峰
文件頁(yè)數(shù)： 8/23頁(yè)
文件大小： 1258K
代理商： TLE6288R
Preliminary Datasheet TLE6288 R
Vp2
Page 8
13.01.2003
4. Pin description:
DOUT 1-3
–
Drain of the 3 highside channels. These pins must always be connected to the same
power (battery) supply line.
SOUT 1-3
– Source of the three highside channels. Outputs of the highside channels where the load is
connected.
DOUT 4-6
–
Drain pins of the three configurable channels. In highside configuration they must be con-
nected to the same voltage as DOUT 1-3. In lowside configuration they are the output pins and con-
nected to the load.
SOUT 4-6
–
Source of the three configurable channels. In highside configuration they are the outputs
and connected to the load. In lowside configuration they must be connected with GND.
IN 1-6
–
Parallel input pins for the 6 power outputs. These pins have an internal pull down structure.
GND
–
Logic ground pin.
FSIN
– Disable pin. If the FSIN pin is in a logic low state, it switches all outputs OFF. An internal pull-up
structure is provided on chip.
Reset
– Reset pin.
When the reset is low all channels are off, the internal biasing is deactivated, all
internal registers are cleared and the supply-current consuption is reduced (standby mode). An internal
pull-up structure is provided on chip.
Fault
– General Fault pin.
There is a general fault pin (open drain) which shows a high to low transition
as soon as an error is latched into the diagnosis register. When the diagnosis register is cleared this
flag is also reset (high state). This fault indication can be used to generate a μC interrupt.
CLKProg
–
Programming pin for the SPI Clock signal.
This pin can be used to configure the clock sig-
nal input of the SPI. In low state the SPI will read data at the rising clock edge and write data at the
falling clock edge. In high state the SPI will read data at the falling clock edge and write data at the ris-
ing clock edge The pin has an internal pull down structure.
DIAG1..5; DIAG6 / Overtemp.
– Parallel diagnostic pins (push-pull) change state according to the in-
put signal of the corresponding channel. As soon as an error occurs at the corresponding channel (
Overload and overtemperature is detected in on state and open load /switch bypass in off state) the
DIAG output shows the inverted input signal. An fault is detected only if it lasts for longer than the fault
filtering time. The fault information is not latched in a register.
If DIAG6 is configured as Overtemperature Flag: This is a general fault pin which shows a high to low
transition as soon as an overtemperature error occurs for any one of the six channels (for longer than
the fault filtering time) or the IC logic. This fault indication can be used to differ between overload and
overtemperature errors in one of the six channels or to detect a general IC overtemperature.
VCP
– Pin to connect the external capacitor of the integrated charge pump.
VDO
– Supply pin of the push-pull digital output drivers. This pin can be used to vary the high-state
output voltage of the SO pin and the DIAG1-6 pins.
VCC
– Logic supply pin. This pin is used to supply the integrated circuitry.
CS
– Chip Select of the SPI
SO
– Signal Output of the
S
erial
P
eripheral
I
nterface
SI
– Signal Input of the
S
erial
P
eripheral
I
nterface. The pin has an internal pull down structure.
SCLK
– Clock Input of the
S
erial
P
eripheral
I
nterface. The pin has an internal pull up structure (if
CLKProg=L) or an pull down structure (if CLKProg=H).
For more details about the SPI see Chapter 9.SPI.
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