參數(shù)資料
型號(hào): TLE6263
廠商: INFINEON TECHNOLOGIES AG
英文描述: LS CAN, LDO and HS Switch
中文描述: 儲(chǔ)蓄的CAN,開關(guān)穩(wěn)壓器和HS
文件頁數(shù): 4/40頁
文件大?。?/td> 811K
代理商: TLE6263
Final Datasheet TLE 6263
Version 2.08
4
2004-06-07
4
Pin Definitions and Functions
Pin No.
Symbol
Function
1
TxD
Transmit data input;
integrated pull up;
LOW: bus becomes dominant, HIGH: bus becomes recessive
2
RxD
Receive data output;
push-pull output;
LOW: bus becomes dominant, HIGH: bus becomes recessive
3
RO
WK2
Reset output
; open drain output, integrated pull up, active low
4
Wake-Up input 2;
for detection of external wake-up events, edge
sensitive, in sleep mode monitored by cyclic sense feature when
selected; weak pull up (2μA) to avoid unwanted wake ups
5
WK1
Wake-Up input 1;
for detection of external wake-up events, edge
sensitive, in sleep mode monitored by cyclic sense feature when
selected; weak pull up (2μA) to avoid unwanted weak ups
6, 7, 8, 9,
20, 21,
22, 23
GND
Ground;
to reduce thermal resistance place cooling areas on
PCB close to this pins.
10
DO
SPI data output
; this tri-state output transfers diagnosis data to
the control device. Serial data transfered from DO is a 8 bit
diagnosis word with the Least Significant Bit (LSB) transmitted
first. The output will remain 3-stated unless the device is selected
by a LOW on Chip-Select-Not (CSN). DO will accept data on the
rising edge of CLK-signal; see
table 4, 5, 6
for Diagnosis protocol
11
CLK
SPI clock input
; clocks the shiftregister; CLK has a pull down
input, active HIGH, and requires CMOS logic level inputs
12
CSN
SPI chip select not input
; CSN is a pull up input, active LOW,
serial communication is enabled by pulling the CSN terminal low;
CSN input should only be transitioned when CLK is low; CSN has
an internal active pull up and requires CMOS logic level inputs
13
DI
SPI data input
; receives serial data from the control device;
serial data transmitted to DI is a 8 bit control word with the Least
Significant Bit (LSB) being transferred first: the input has a pull
down input, active HIGH, and requires CMOS logic level inputs;
DI will accept data on the falling edge of CLK-signal; see
table 3
for input data protocol
14
OUTHS
High side switch output;
controlled via SPI, in sleep mode
controlled by internal cyclic sense function when selected
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