參數(shù)資料
型號(hào)： TLC5941RHB
廠商： Texas Instruments, Inc.
英文描述： 16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL
中文描述： 16-CHANNEL的LED驅(qū)動(dòng)器，帶有點(diǎn)校正與灰度PWM控制
文件頁(yè)數(shù)： 15/23頁(yè)
文件大?。?/td> 513K
代理商： TLC5941RHB
www.ti.com
GS 15.11
191
GS 14.11
178
GS 0.11
11
GS 0.0
0
GS15.0
180
GS 0.0
12
LSB
MSB
GS OUT0
GS OUT15
GS OUT2 GS OUT14
t
su2
SCLK
SOUT
SIN
MODE
GS
MSB
1
Following GS Mode Data
Input Cycle
XLAT
DC
LSB
96
DC Mode Data
Input Cycle
192
GS
LSB
193
GS + 1
MSB
1
DC n
LSB
DC
MSB
GS
MSB
SID
MSB
SID
MSB1
First GS Mode Data
Input Cycle After DC Data Input Cycle
192
SID n + 1
MSB
GS n + 1
LSB
t
h3
t
su3
t
h1
t
h2
t
su1
t
wh2
t
h3
X
X
SID
LSB
t
pd0
STATUS INFORMATION OUTPUT
The TLC5941 does have a status information register, which can be accessed in grayscale mode (MODE =
GND). After the XLAT signal latches the data into the GS register, the input shift register data is replaced with
status information data (SID) of the device (see
Figure 10
). LOD, TEF, and dot-correction register data can be
read out at the SOUT pin. The status information data packet is 192 bits wide. Bits 176 – 191 contain the LOD
status of each channel. Bit 175 contains the TEF status. Bits 72 – 167 contain the data of the dot-correction
register. The remaining bits are reserved. The complete status information data packet is shown in
Figure 11
.
LOD 15
LOD 0
TEF
X
X
DC15.5
DC 0.0
X
X
191
176
175
168
167
72
71
0
MSB
LSB
LOD Data
TEF
DC Values
Reserved
TLC5941
SLVS589–JULY 2005
Figure 9. Grayscale Data Packet Format
When MODE is set to GND, the TLC5941 enters the grayscale data input mode. The device switches the input
shift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal latches the data into
the grayscale register (see
Figure 10
). The first GS data input cycle after dot correction requires an additional
SCLK pulse after the XLAT signal to complete the grayscale update cycle. All GS data in the input shift register
is replaced with status information data (SID) after latching into the grayscale register.
Figure 10. Grayscale Data Input Timing Chart
Figure 11. Status Information Data Packet Format
15
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