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參數(shù)資料
| 型號(hào)： | TLC34075-110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁(yè)數(shù)： | 29/52頁(yè) |
| 文件大?。?/td> | 284K |
| 代理商： | TLC34075-110 |
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FUNCTION
2
–
17
Table 8. General Control Register Bit Functions
GENERAL CONTROL REGISTER BIT
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
1
X
0
X
X
1
X
0
X
X
1
X
X
X
X
X
X
X
X
7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
3
X
X
X
X
X
0
0
1
X
X
X
X
X
X
X
X
2
X
X
X
X
0
1
X
0
X
X
X
X
X
X
X
X
1
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HSYNCOUT is active-low
HSYNCOUT is active-high (default)
VSYNCOUT is active-low
VSYNCOUT is active-high (default)
Disable split shift register transfer (default)
Enable split shift register transfer
Disable special nibble mode (default)
Enable special nibble mode
0-IRE pedestal (default)
7.5-IRE pedestal
Disable sync (default)
Enable sync
Reserved (default)
Reserved
MUXOUT is low (default)
MUXOUT is high
2.11.1
HSYNCOUT and VSYNCOUT polarity inversion is provided to allow indication to monitors of the current
screen resolution. Since the polarities for VGA pass-through mode are provided at the feature connector,
the inputs to the TLC34075 will have the right polarities for monitors already, so the TLC34075 just passes
them through with pipeline delay (see Section 2.8). These two bits only work in the normal modes, and the
input horizontal and vertical syncs are assumed to be active-low incoming pulses. These two bits default
to the value 1 but can be changed by software.
HSYNCOUT and VSYNCOUT (Bits 0 and 1)
2.11.2
Split Shift Register Transfer Enable (SSRT) and Special Nibble Mode Enable
(SNM) (Bits 2 and 3)
See Section 2.9.
2.11.3
This bit specifies whether a 0- or 7.5-IRE blanking pedestal is to be generated on the video outputs. Having
a 0-IRE blanking pedestal means that the black and blank levels are the same.
Pedestal Enable Control (Bit 4)
0: 0-IRE pedestal (default)
1: 7.5-IRE pedestal
2.11.4
This bit specifies whether or not SYNC information is to be output onto IOG.
Sync Enable Control (Bit 5)
0: Disable sync (default)
1: Enable sync
2.11.5
The MUXOUT bit indicates to external circuitry that the device is running in VGA pass-through mode. This
bit does not affect the operation of the device (see Section 2.10).
MUXOUT (Bit 7)
0: MUXOUT is low (default in VGA pass-through mode)
1: MUXOUT is high
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC34075-135 | Video Interface Palette |
| TLC34075-66 | Video Interface Palette |
| TLC34075-85 | Video Interface Palette |
| TLC352MFK | LinCMOSE DUAL DIFFERENTIAL COMPARATOR |
| TLC352MJG | LinCMOSE DUAL DIFFERENTIAL COMPARATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC34075-110AFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TLC34075-135 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TLC34075-135AFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TLC34075-135AFNR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual |
| TLC34075-135FN | 制造商:Texas Instruments 功能描述:1024 X 768 PIXELS PALETTE-DAC DSPL CTLR, PQCC84 |
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