參數(shù)資料
型號： TLC34075-110
廠商： Texas Instruments, Inc.
英文描述： Video Interface Palette
中文描述： 視頻接口面板
文件頁數(shù)： 23/52頁
文件大?。?/td> 284K
代理商： TLC34075-110
2
–
11
As an example of how to use Table 6, suppose that the design goals specify a system with eight data bits
per pixel and the lowest possible SCLK rate. Table 6 shows that, for non-VGA-pass-through operation, only
mode 4 supports an eight-bit pixel depth. The lowest-possible SCLK rate within mode 4 is 1:4. This set of
conditions is selected by writing the value 1Eh to the mux control register. The pixel latching sequence
column shows that, in this mode, P<7:0> should be connected to the earliest-displayed pixel plane, followed
by P<15:8>, P<23:16>, and then P<31:24> as the last displayed pixel plane. Assuming that VCLK is
programmed as DOTCLK/4, Table 2
–
5 shows that the 1:4 SCLK ratio is selected by writing the value 12h
to the output clock selection register. The special nibble mode should also be disabled (see Sections 2.9.2
and 2.11.2).
When the mux control register is loaded with 2Dh, the TLC34075 enters the VGA pass-through mode (the
same condition as the default power-up mode). Please refer to Section 2.5.4 for more details.
2.4.6
The read mask register is used to enable or disable a pixel address bit from addressing the color palette
RAM. Each palette address bit is logically ANDed with the corresponding bit from the read mask register
before addressing the palette. This function is performed after the addition of the page register bits and,
therefore, a zeroing of the read mask results in one unique palette location (location 0) and is not affected
by the palette page register contents.
Read Masking
2.5
There are 3 ways to reset the TLC34075:
Reset
1.
2.
3.
Power-on reset
Hardware reset
Software reset
2.5.1
The TLC34075 contains a power-on reset circuit. Once the voltage levels have stabilized following power-on
reset, the device is in the VGA pass-through mode.
Power-On Reset
2.5.2
The TLC34075 resets whenever RS<3:0> = HHHH and a rising edge occurs on the WR input. The more
rising WR edges occur, the more reliable the TLC34075 is reset. This scheme (bursting WR strobes until
the power supply voltage stablizes) is suggested at power-up if a hardware reset approach is used.
Hardware Reset
The default reset condition is VGA pass-through mode, and the values for each register are shown in
Section 2.5.4.
2.5.3
Whenever the mux control register is set for VGA pass-through mode after power-up, all registers are
initialized accordingly. Since VGA pass-through mode is the default condition at power-up and hardware
reset, the act of selecting the VGA pass-through mode through programming the mux control register is
viewed as a software reset. Therefore, whenever mux control register bits <5:0> are set to 2Dh, the
TLC34075 initiates a software reset.
Software Reset
2.5.4
The value contained in each register after hardware or software reset is shown below:
VGA Pass-Through Mode Default Conditions
Mux control register:
Input clock selection register:
Output clock selection register:
Palette page register:
General control register:
2Dh
00h
3Fh
00h
03h
相關(guān)PDF資料
PDF描述
TLC34075-135 Video Interface Palette
TLC34075-66 Video Interface Palette
TLC34075-85 Video Interface Palette
TLC352MFK LinCMOSE DUAL DIFFERENTIAL COMPARATOR
TLC352MJG LinCMOSE DUAL DIFFERENTIAL COMPARATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC34075-110AFN 制造商:Rochester Electronics LLC 功能描述:- Bulk
TLC34075-135 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TLC34075-135AFN 制造商:Rochester Electronics LLC 功能描述:- Bulk
TLC34075-135AFNR 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual
TLC34075-135FN 制造商:Texas Instruments 功能描述:1024 X 768 PIXELS PALETTE-DAC DSPL CTLR, PQCC84
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