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參數(shù)資料
| 型號： | TLC320AD81CDBTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), EQUALIZER CIRCUIT, PDSO38 |
| 封裝： | PLASTIC, TSSOP-38 |
| 文件頁數(shù)： | 4/47頁 |
| 文件大?。?/td> | 195K |
| 代理商： | TLC320AD81CDBTR |
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1–4
1.5
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AVDD_DAC
21
I
Analog power supply for the DAC
AVDD_PLL
6
I
Analog power supply for the PLL
AVSS_DAC
18
I
Analog ground for the DAC
AVSS_PLL
5
I
Analog ground for the PLL
CAP_VREF
14
O
10
F // 0.1 F to AVSS_DAC (recommended values)
CS1
31
I
I2C address bit A0; low = 0, high = 1
CS2
32
I
I2C address bit A1; low = 0, high = 1
DM
29
I
De-emphasis at 44.1 kHz; off when pin low, on when pin high (default = on
when pin not driven or biased)
DVDD
34
I
Digital power supply
DVDD_DAC
20
I
Digital power supply for the DAC
DVSS
33
I
Digital ground
DVSS_DAC
19
I
Digital ground for the DAC
LRCLK
3
I
Serial audio left/right clock sampling frequency (fs)
MCLK
2
I
Master clock
NC
11–13 15, 17,
23, 24 26–28
No connection
OUT_L
22
O
Analog output voltage left channel
OUT_R
16
O
Analog output voltage right channel
PLL–FLT
7
O
C1 = 1500 pF // R1 = 27.4
+ C2 = 0.068 F (recommended values)
RESERVED
8, 9, 30
For internal use only, must be connected to GND
RESET
10
I
Reset, low = current state, high = reinitialized the device
SCL
36
I/O
Slave serial I2C clock
SCLK
4
I
Shift clock (bit clock)
SDA
35
I/O
Slave serial I2C data
SDIN1
37
I
Serial audio data input one
SDIN2
38
I
Serial audio data input two
SDOUT
1
O
Serial audio data output
SMUTE
25
I
Soft mute off when pin low; on when pin high (default = off when pin not
driven or biased)
If only one capacitor is used, a 10-
F capacitor connected to AVSS_DAC should be used.
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