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參數(shù)資料
| 型號： | TLC320AD57CDWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SO-28 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 129K |
| 代理商： | TLC320AD57CDWR |
2–6
2.8.2
Slave Mode
As a slave, the TLC320AD57C receives LRClk, Fsync, and SCLK as inputs. The conversion cycle
synchronizes to the rising edge of LRClk, and the data synchronizes to the falling edge of SCLK. SCLK must
meet the setup time requirements specified in Section 3.2, Recommended Operating Conditions.
Synchronization of the slave modes is accomplished with the digital power-down control.
In slave mode, Fsync is an input. Three modes are provided as shown in Figures 2–4(a) through 2–4(c).
SCLK and LRClk are externally generated and sourced. The first rising edges of SCLK and LRClk after a
power-down cycle initiate the conversion cycle. Refer to Section 2.8.1, Master Mode for signal functions.
Several modes are available when the TLC320AD57C is configured as a slave. Using the Mode0, Mode1,
and Mode2 terminals, the TLC320AD57C can be set to shift out the MSB first or the LSB first [see Figures
2–4(a) and 2–4(b)]. The number of bits shifted out can be controlled by the number of valid SCLK cycles
provided within the left or right channel period. If only enough clocks are provided to shift out 16 data bits
before LRClk changes state, this is equivalent to a 16-bit mode.
. . .
17
16
. . .
10
17
16
. . .
10
SCLK
Fsync
DOUT
input
LRClk
Mode 000
(a) SLAVE MODE (Fsync high)
(b) SLAVE MODE (Fsync high)
SCLK
Fsync
DOUT
LRClk
Mode 001
input
output
input
01
. . .
16
01
. . .
16
17
64 SCLKs
17
. . .
017
. . .
0
17
. . .
0
17
0
32 – 128 SCLKs
(c) SLAVE MODE (Fsync controlled)
SCLK
Fsync(1)
DOUT(1)
Mode 010
LRClk
Fsync(2)
DOUT(2)
Left
Right
Left
32 – 128 SCLKs
Right
Figure 2–4. Serial Slave Transfer Modes
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