參數(shù)資料
型號(hào): TLC320AC02IPM
廠商: TEXAS INSTRUMENTS INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, QFP-64
文件頁數(shù): 41/86頁
文件大?。?/td> 471K
代理商: TLC320AC02IPM
3–8
3.6
Timing Requirements and Specifications in Master Mode
3.6.1
Recommended Input Timing Requirements for Master Mode, VDD = 5 V
MIN
NOM
MAX
UNIT
tr(MCLK)
Master clock rise time
5
ns
tf(MCLK)
Master clock fall time
5
ns
Master clock duty cycle
40%
60%
tw(RESET)
RESET pulse duration
1 MCLK
tsu(DIN)
DIN setup time before SCLK low (see Figure 4–2)
25
ns
th(DIN)
DIN hold time after SCLK low (see Figure 4–2)
20
ns
3.6.2
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, VDD = 5 V (Unless Otherwise Noted) (see Note 23)
PARAMETER
MIN
TYP
MAX
UNIT
tf(SCLK)
Shift clock fall time (see Figure 4–2)
13
18
ns
tr(SCLK)
Shift clock rise time (see Figure 4–2)
13
18
ns
Shift clock duty cycle
45%
55%
td(CH-FL)
Delay time from SCLK high to FSD low
(see Figures 4–2 and 4–4 and Note 24)
5
20
ns
td(CH-FH)
Delay time from SCLK high to FS high (see Figure 4–2)
5
20
ns
td(CH-DOUT)
Delay time from SCLK high to DOUT valid
(see Figures 4–2 and 4–7)
20
ns
td(CH-DOUTZ)
Delay time from SCLK
↑ to DOUT in high-impedance state
(see Figure 4–8)
20
ns
td(ML-EL)
Delay time from MCLK low to EOC low (see Figure 4–9)
40
ns
td(ML-EH)
Delay time from MCLK low to EOC high (see Figure 4–9)
40
ns
tf(EL)
EOC fall time (see Figure 4–9)
13
ns
tr(EH)
EOC rise time (see Figure 4–9)
13
ns
td(MH-CH)
Delay time from MCLK high to SCLK high
50
ns
td(MH-CL)
Delay time from MCLK high to SCLK low
50
ns
All typical values are at VDD = 5 V and TA = 25°C.
NOTES: 23. All timing specifications are valid with CL = 20 pF.
24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.
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