參數(shù)資料
型號(hào)： TLC320AC02IPM
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, QFP-64
文件頁(yè)數(shù)： 33/86頁(yè)
文件大?。?/td> 471K
代理商： TLC320AC02IPM
3–1
3
Specifications
3.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)
Supply voltage range, DGTL VDD (see Notes 1 and 2)
– 0.3 V to 6.5 V
. . . . . . . . . . . . . . .
Supply voltage range, DAC VDD (see Notes 1 and 2)
– 0.3 V to 6.5 V
. . . . . . . . . . . . . . . .
Supply voltage range, ADC VDD (see Notes 1 and 2)
– 0.3 V to 6.5 V
. . . . . . . . . . . . . . . .
Differential supply voltage range, DGTL VDD to DAC VDD
– 0.3 V to 6.5 V
. . . . . . . . . . . .
Differential supply voltage range, all positive supply voltages to
ADC GND, DAC GND, DGTL GND, SUBS
– 0.3 V to 6.5 V
. . . . . . . . . . . . . . . . . . . .
Output voltage range, DOUT
– 0.3 V to DGTL VDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, DIN
– 0.3 V to DGTL VDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground voltage range, ADC GND, DAC GND,
DGTL GND, SUBS
– 0.3 V to DGTL VDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA
0
°C to 70°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
–40
°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
. . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
3.2
Recommended Operating Conditions (see Note 2)
MIN
NOM
MAX
UNIT
VDD
Positive supply voltage
4.5
5
5.5
V
Steady-state differential voltage between any two supplies
0.1
V
VIH
High-level digital input voltage
2.2
V
VIL
Low-level digital input voltage
0.8
V
IO
Load output current from ADC VMID and DAC
100
A
Conversion time for the ADC and DAC channels
10 FCLK periods
fMCLK
Master-clock frequency
10.368
15
MHz
VID(PP)
Analog input voltage (differential, peak to peak)
6
V
RL
Differential output load resistance
600
RL
Single-ended to buffered DAC VMID voltage load resistance
300
TA
Operating free-air temperature
0
70
°C
NOTES:
1. Voltage values for DGTL VDD are with respect to DGTL GND, voltage values for DAC VDD are with respect
to DAC GND, and voltage values for ADC VDD are with respect to ADC GND. For the subsequent electrical,
operating, and timing specifications, the symbol VDD denotes all positive supplies. DAC GND, ADC GND,
DGTL GND, and SUBS are at 0 V unless otherwise specified.
2. To avoid possible damage to these CMOS devices and associated operating parameters, the sequence
below should be followed when applying power:
(1) Connect SUBS, DGTL GND, ADC GND, and DAC GND to ground.
(2) Connect voltages ADC VDD,and DAC VDD.
(3) Connect voltage DGTL VDD.
(4) Connect the input signals.
When removing power, follow the steps above in reverse order.
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