參數(shù)資料
型號: TLC2554CPW
廠商: Texas Instruments, Inc.
英文描述: 5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
中文描述: 5五,12位400 ksps的,4 / 8通道,低功耗,串行模數(shù)位自動開機和下變頻器
文件頁數(shù): 20/37頁
文件大小: 566K
代理商: TLC2554CPW
TLC2554, TLC2558
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A –JUNE 1999
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (continued)
MIN
0.5
NOM
MAX
UNIT
SCLK
Transition time, for FS, SCLK, SDI, tt(CLK)
Setup time, CS falling edge before SCLK rising edge (FS=1) or before SCLK falling edge (when FS is active),
tsu(CS-SCLK)
Hold time, CS rising edge after SCLK rising edge (FS=1) or after SCLK falling edge (when FS is active),
th(SCLK-CS)
Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH)
Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS is active), td(SCLK16F-CSH)
Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKF)
Hold time, FS hold high after SCLK falling edge, th(FSH-SCLKF)
Pulse width, CS high time, twH(CS)
SCLK cycle time, VCC = 2.7 V to 3.6V, tc(SCLK)
SCLK cycle time, VCC = 4.5 V to 5.5V, tc(SCLK)
Pulse width, SCLK low time, twL(SCLK)
Pulse width, SCLK high time, twH(SCLK)
Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1),
tsu(DI-SCLK)
Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1),
th(DI-SCLK)
Delay time, delay from CS falling edge to SDO valid, td(CSL-DOV)
Delay time, delay from FS falling edge to SDO valid, td(FSL-DOV)
Delay time, delay from SCLK rising edge (FS is active) or SCLK falling edge (FS=1) SDO valid, td(CLK-DOV)
Delay time, delay from CS rising edge to SDO 3-stated, td(CSH-DOZ)
Delay time, delay from 16th SCLK falling edge (FS is active) or the 16th rising edge (FS=1) to EOC falling
edge, td(CLK-EOCL)
Delay time, delay from EOC rising edge to SDO 3-stated if CS is low, td(EOCH-DOZ)
Delay time, delay from 16th SCLK rising edge to INT falling edge (FS =1) or from the 16th falling edge SCLK
to INT falling edge (when FS active), td(SCLK-INTL)
Delay time, delay from CS falling edge to INT rising edge, td(CSL-INTH)
Delay time, delay from CS rising edge to CSTART falling edge, td(CSH-CSTARTL)
Delay time, delay from CSTART rising edge to EOC falling edge, td(CSTARTH-EOCL)
Pulse width, CSTART low time, twL(CSTART)
Delay time, delay from CS rising edge to EOC rising edge, td(CSH-EOCH)
Delay time, delay from CSTART rising edge to CSTART falling edge, td(CSTARTH-CSTARTL)
Delay time, delay from CSTART rising edge to INT falling edge, td(CSTARTH-INTL)
0.5
SCLK
5
ns
0.5
0.5
7
SCLKs
SCLKs
SCLKs
SCLKs
ns
ns
ns
ns
ns
0.5
0.5
100
67
50
20
20
30
30
25
ns
5
ns
1
1
1
1
25
25
25
25
ns
ns
ns
ns
1
25
ns
1
50
ns
3.5
μ
s
1
50
ns
ns
ns
μ
s
ns
μ
s
μ
s
100
1
50
0.8
1
50
3.6
3.5
Operating free air temperature TA
TLC2554C/TLC2558C
TLC2554I/TLC2558I
0
70
85
C
–40
NOTE 2: This is the time required for the clock input signal to fall from VIH max or to rise from VILmax to VIHmin. In the vicinity of normal room
temperature, the devices function with input clock transition time as slow as 1
μ
s for remote data-acquisition applications where the
sensor and A/D converter are placed several feet away from the controlling microprocessor.
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