參數(shù)資料
型號: TLC2554CPW
廠商: Texas Instruments, Inc.
英文描述: 5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
中文描述: 5五,12位400 ksps的,4 / 8通道,低功耗,串行模數(shù)位自動開機和下變頻器
文件頁數(shù): 11/37頁
文件大小: 566K
代理商: TLC2554CPW
TLC2554, TLC2558
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A –JUNE 1999
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
read cycle (read FIFO or read CFR) (continued)
FIFO read cycle
The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read
command. The first FIFO content is output immediately before the command is decoded. If this command is
not a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO read
command is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This is
because the read cycle does not generate EOC or INT nor does it carry out any conversion.
INT
SCLK
CS
FS
SDI
EOC
SDO
ID15
ID14
ID13
ID12
ID14
OD8
OD7
OD5
OD0
1
2
3
4
5
6
7
13
14
15
16
1
12
OD11 OD10
OD9
ID15
OD6
Figure 4. TLC2554/TLC2558 Continuous FIFO Read Cycle (FS = 1)
(controlled by SCLK, SCLK can stop between each 16 SCLKs)
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