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參數(shù)資料
| 型號： | TLC1225MFKR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CQCC28 |
| 封裝： | CERAMIC, LCC-28 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 230K |
| 代理商： | TLC1225MFKR |
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOL
VCC
CL
RL
Data Output
DGTL
VCC
RD
VCC
DGTL
Data Output
RL
CL
90%
Data Output
10%
90%
10%
50%
tdis
VCC
RD
GND
Data Output
VOH
GND
RD
VCC
tdis
50%
10%
90%
Figure 4. Load Circuits and Waveforms
APPLICATION INFORMATION
unipolar and bipolar operation
For single-ended signal input, the IN+ input is connected to the analog source and the IN– input is connected
to ANLG GND. In the unipolar configuration, the ADC uses a single 5-V supply and the analog input voltage
range is 0 V to 5 V. Data bit D12 always remains low. In the bipolar configuration, the ADC uses
±5-V supplies
and the analog input voltage range is – 5 V to 5 V. Data bit D12 indicates the sign of the input signal. In both
configurations, the 13-bit data format is extended sign with 2s-complement, right-justified data.
power-up sequence
Calibration is not automatic on power up. Calibration is initiated by writing control words to the six least significant
bits of the data bus. Vref must have fully settled before calibration is initiated. If addressed or initiated, conversion
can begin after the first clock cycle; however, full A/D conversion accuracy is not established until after internal
capacitor calibration.
conversion period start sequence
The writing of the conversion command word to the six least significant bits of the data bus when either CS or
WR goes high initiates the conversion sequence.
analog sampling sequence
Sampling of the input signal occurs during clock cycles 3 through 10 of the conversion sequence.
completed A/D conversion
When INT goes low, conversion is complete and the A/D result can be read. A new conversion period can begin
immediately. The A/D conversion is complete at the end of clock cycle 24 of the conversion period.
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