參數(shù)資料
型號： THS8200PFPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： GREEN, PLASTIC, HTQFP-80
文件頁數(shù)： 12/101頁
文件大?。?/td> 806K
代理商： THS8200PFPG4
4–3
Y7(0)
Y6(0)
Y5(0)
Y4(0)
Y3(0)
Y2(0)
Y1(0)
Y7(1)
Y6(1)
Y5(1)
Y4(1)
Y3(1)
Y2(1)
Y1(1)
Y7(2)
Y6(2)
Y5(2)
Y4(2)
Y3(2)
Y2(2)
Y1(2)
Y7(3)
Y6(3)
Y5(3)
Y4(3)
Y3(3)
Y2(3)
Y1(3)
GY[9]
GY[8]
GY[7]
GY[6]
GY[5]
GY[4]
GY[3]
GY[2]
Cb7(0)
Cb6(0)
Cb5(0)
Cb4(0)
Cb3(0)
Cb2(0)
Cb1(0)
Cb0(0)
Cr7(0)
Cr6(0)
Cr5(0)
Cr4(0)
Cr3(0)
Cr2(0)
Cr1(0)
Cr0(0)
Cb7(2)
Cb6(2)
Cb5(2)
Cb4(2)
Cb3(2)
Cb2(2)
Cb1(2)
Cb0(2)
Cr7(2)
Cr6(2)
Cr5(2)
Cr4(2)
Cr3(2)
Cr2(2)
Cr1(2)
Cr0(2)
BCb[9]
BCb[8]
BCb[7]
BCb[6]
BCb[5]
BCb[4]
BCb[3]
BCb[2]
X
RCr[9]
RCr[8]
RCr[7]
RCr[6]
RCr[5]
RCr[4]
RCr[3]
RCr[2]
CLKIN
Data
Manager
Cb7(0)
Cb6(0)
Cb5(0)
Cb4(0)
Cb3(0)
Cb7(2)
Cb6(2)
Cb5(2)
Cb4(2)
Cb3(2)
TO CH1
TO CH2
TO CH3
Y7(0)
Y6(0)
Y5(0)
Y4(0)
Y3(0)
Y2(0)
Y1(0)
Y6(1)
Y7(2)
Y6(2)
Y5(2)
Y4(2)
Y3(2)
Y2(2)
Y1(2)
Y7(3)
Y6(3)
Y5(3)
Y4(3)
Y3(3)
Y2(3)
Y1(3)
Cb2(0)
Cb1(0)
Cb0(0)
Cb2(2)
Cb1(2)
Cb0(2)
Cr7’(1)
Cr7(2)
Cr6(2)
Cr5(2)
Cr4(2)
Cr3(2)
Cr6’(1)
Cr5’(1)
Cr4’(1)
Cr3’(1)
Cr2’(1)
Cr1’(0)
Cr0’(1)
Cr2(2)
Cr1(2)
Cr0(2)
Cr7(0)
Cr6(0)
Cr5(0)
Cr4(0)
Cr3(0)
Cr2(0)
Cr1(0)
Cr0(0)
Cr7’(3)
Cr6’(3)
Cr5’(3)
Cr4’(3)
Cr3’(3)
Cr2’(3)
Cr1’(3)
Cr0’(3)
Y7(1)
Y5(1)
Y4(1)
Y3(1)
Y2(1)
Y1(1)
Cb7’(1)
Cb5’(1)
Cb4’(1)
Cb3’(1)
Cb2’(1)
Cb1’(1)
Cb0’(1)
Cb6’(1)
Cb7’(3)
Cb6’(3)
Cb5’(3)
Cb4’(3)
Cb3’(3)
Cb2’(3)
Cb1’(3)
Cb0’(3)
NOTE: Where Cb’Cr’ are the output of half-band interpolation filter.
Figure 4–2. 20-/16-Bit YCbCr 4:2:2 Data Format (16-Bit Operation Shown)
When dedicated timing is used in this mode, there is a fixed relationship between the first active period of HS_IN (i.e.,
the first CLKIN rising edge seeing HS_IN active) and a Cb color component assumed present during that clock period
on the bus receiving CbCr samples. When embedded timing is used in this mode, the SAV/EAV structure also
unambiguously defines the CbCr sequence, according to SMPTE274M/296M for HDTV.
NOTE: The figure shows the case when only 8 bits of each 10-bit input bus are used.
10-bit YCbCr 4:2:2 (ITU mode)
CLKIN is equal to 2
× the pixel clock since all components are multiplexed on a single 10-bit bus with a 4-multiple
sequence: CbYCrY. Therefore the pixel clock (i.e., the Y input rate) is 1/2 of CLKIN and the Cb and Cr rate are 1/4
of CLKIN.
相關(guān)PDF資料
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THS8210PFP SPECIALTY CONSUMER CIRCUIT, PQFP80
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