參數(shù)資料
型號(hào)： THS8136IPHPR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48
封裝： PLASTIC, TQFP-48
文件頁(yè)數(shù)： 2/18頁(yè)
文件大小： 377K
代理商： THS8136IPHPR
SLES236A – NOVEMBER 2008 – REVISED DECEMBER 2010
www.ti.com
POWER SUPPLY ELECTRICAL CHARACTERISTICS
over recommended operating conditions, fCLK = 180 MHz, use of internal reference voltage VREF, RFS = RFS(nom),
37.5-
load termination (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP(2)
MAX(3)
UNIT
CLK = 80 MSPS
65
72
Generic (700 mV)
CLK = 180 MSPS
65
72
CLK = 80 MSPS
110
112
Operating supply current,
IAVDD
Generic (1.2 mV)
mA
analog
CLK = 180 MSPS
110
112
CLK = 80 MSPS
94
102
Sync Insertion (700 mV + Sync)
CLK = 180 MSPS
94
103
CLK = 80 MSPS
13
16
Generic (700 mV)
CLK = 180 MSPS
31
36
CLK = 80 MSPS
14
16
Operating supply current,
IDVDD
Generic (1.2 mV)
mA
digital
CLK = 180 MSPS
31
37
CLK = 80 MSPS
13
16
Sync Insertion (700 mV + Sync)
CLK = 180 MSPS
31
36
CLK = 80 MSPS
238
290
Generic (700 mV)
CLK = 180 MSPS
270
329
CLK = 80 MSPS
388
434
PD
Power dissipation
Generic (1.2 mV)
mW
CLK = 180 MSPS
419
475
CLK = 80 MSPS
334
398
Sync Insertion (700 mV + Sync)
CLK = 180 MSPS
366
441
(1)
A multiburst RGB input test pattern was used in all cases.
(2)
TYP current and PD measured at AVDD = 3.3 V and DVDD = 1.8 V.
(3)
MAX current and PD measured at AVDD = 3.6 V and DVDD = 1.95 V.
DIGITAL INPUTS – DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions, fCLK = 180 MHz, use of internal reference voltage VREF, RFS = RFS(nom),
37.5-
load termination (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level input current
AVDD = 3.3 V, DVDD = 1.8 V, Digital inputs at 1.95 V
1
mA
IIL
Low-level input current
AVDD = 3.3 V, DVDD = 1.8 V, Digital inputs at 0 V
–1
mA
IIH(CLK)
High-level input current, CLK
AVDD = 3.3 V, DVDD = 1.8 V, CLK at 1.95 V
–1
1
mA
IIL(CLK)
Low-level input current, CLK
AVDD = 3.3 V, DVDD = 1.8 V, CLK at 0 V
–1
1
mA
CI
Input capacitance
TA = 25°C
5
pF
Setup time, data and control
ts
1.5
ns
inputs(1)
Hold time, data and control
th
500
ps
inputs(1)
Digital process delay time from first
CLK
td(D)
registered color component of
7.5
periods
pixel(2)
(1)
Specified by characterization only.
(2)
This parameter is specified by design. The digital process delay is defined as the number of CLK cycles required for the first registered
color component of a pixel, starting from the time of registering it on the input bus, to propagate through all processing and appear at the
DAC output drivers. The remaining delay through the IC is the analog delay td(A) of the analog output drivers.
10
Copyright 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): THS8136
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