參數(shù)資料
型號: THS8135-80IPHP
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48
封裝: POWER, TQFP-48
文件頁數(shù): 18/24頁
文件大?。?/td> 546K
代理商: THS8135-80IPHP
THS8135
TRIPLE 10-BIT, 80/240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601)
– COMPLIANT FULL SCALE RANGE
SLVSXXXX—10/02/00 3:44 PM
4
Copyright 2000 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
M1
47
I
Operation Mode Control 1. The second rising edge on CLK after a transition on
/SYNC latches M1. The interpretation is dependent on the polarity of the last
/SYNC transition:
/SYNC L->H: latched as M1_INT
/SYNC H->L: latched as BLNK_INT.
Together with M2_INT, M1_INT configures the device as shown in Table 4.
BLNK_INT determines if the device operates with the full or reduced scale
range, which also determines the amplitude of the blanking level on the analog
output(s) as shown in Table 7.
M2
48
I
Operation Mode Control 2. The second rising edge on CLK after a transition on
/SYNC latches M2. The interpretation is dependent on the polarity of the last
/SYNC transition:
/SYNC L->H: latched as M2_INT
/SYNC H->L: latched as INS3_INT
Together with M1_INT, M2_INT configures the device as shown in Table 5.
When INS3_INT is high, the sync output is inserted on all DAC outputs; a low
will insert it only on the AGY output.
ARPr
43
O
AGY
41
O
ABPb
45
O
Analog Red, Green and Blue resp. Pr, Y and Pb Current Outputs, capable of
directly driving a doubly terminated 75
coaxial cable.
FSADJ
38
I
Full-scale adjust control. The full scale current drive on each of the output
channels is determined by the value of a resistor R
FS connected between this
terminal and AVSS. The nominal value of R
FS is TBD .This value produces
the nominal full-scale currents of Table 11.The relationship between R
FS and
the full-scale current level for each operation mode is explained in the
functional description.
COMP
39
O
Compensation terminal. A 0.1 uF capacitor must be connected between
COMP and AVDD.
DVDD
12
I
Digital Power Supply (1.8V).
DVSS
11
I
Digital Ground
VREF
37
I/O
Voltage Reference for DACs. An internal voltage reference of nominally 1.2V is
provided, which requires an external 0.1uF ceramic capacitor between VREF
and AVSS. However, the internal reference can be overdriven by an externally
supplied reference voltage.
AVDD
40,44
I
Analog Power Supply (3.3V). All AVDD pins must be connected.
AVSS
42,46
I
Analog Ground
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