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參數(shù)資料
| 型號(hào)： | THS8135-80IPHP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48 |
| 封裝： | POWER, TQFP-48 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 546K |
| 代理商： | THS8135-80IPHP |
THS8135
TRIPLE 10-BIT, 80/240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO
(ITU-R.BT601) – COMPLIANT FULL SCALE RANGE
SLVSXXXX—10/02/00 3:44 PM
3
Copyright 2000 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
Table 1: Available Options
T
A
PACKAGED DEVICES:
TQFP-48 PowerPAD
TM
0
°C to 70°C
THS8135-80CPHP
-40
°C to 85°C
THS8135-80IPHP
0
°C to 70°C
THS8135-240CPHP
-40
°C to 85°C
THS8135-240IPHP
Table 2: Terminal description
Name
Pin #
Terminal Description
RPr0-RPr9
13-22
I
GY0-GY9
36-27
I
BPb0-BPb9
10-1
I
Red, Green and Blue resp. Pr, Y and Pb Pixel Data Inputs. Signals with index 0
denote the least significant bits. Refer to functional description for different
operating modes.
CLK
26
I
Clock input. A rising edge on CLK latches RPr0-9,GY0-9,BPb0-9,/BLANK,
/SYNC and SYNC_T. The M1 & M2 inputs are latched by a rising edge on CLK
as well but only when additional conditions are satisfied, as explained in its
terminal description.
/BLANK
23
I
Blanking Control Input, active low. A rising edge on CLK latches /BLANK.
When asserted, the ARPr, AGY and ABPb outputs are driven to the blanking
level, irrespective of the value on the data inputs. /SYNC takes precedence
over /BLANK so asserting /SYNC (low) while /BLANK is active (low) will result
in sync generation. The analog amplitude of the DAC outputs during /BLANK
active are determined by the operation mode of the device. /BLANK control is
available in both video and generic modes (see functional description).
/SYNC
24
I
Sync Control Input, active low. A rising edge on CLK latches /SYNC. When
asserted, only the AGY output (INS3_INT=L, see terminal M2) or ARPr, AGY &
ABPb outputs (INS3_INT=H, see terminal M2) are driven to the sync level,
irrespective of the values on the data or /BLANK inputs. Consequently, /SYNC
should remain low for the whole duration of sync, which is thus in the case of a
trilevel sync both the negative and positive portion. See also Figure 6. /SYNC
control is only available in video mode (see functional description).
SYNC_T
25
I
Sync Trilevel Control, active high. A rising edge on CLK latches SYNC_T.
When asserted, a positive sync (higher than blanking level) is generated when
/SYNC is low. When disabled, a negative sync (lower than blanking level) is
generated when /SYNC is low. When generating a trilevel (negative-to-positive)
sync, a L->H transition on this signal positions the start of the positive
transition. See Figure 6 for timing control.
When /SYNC is not asserted (high) the value of SYNC_T determines video vs.
generic mode of the device (see functional description).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THS8135EVM | 功能描述:視頻 IC 開發(fā)工具 Triple 10B 240MSPS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評(píng)估:LMH1251 工作電源電壓:5 V |
| THS8135PHP | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 Triple 10B 240MSPS Video DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
| THS8135PHP | 制造商:Texas Instruments 功能描述:10BIT DAC 240MSPS TRIPLE SMD |
| THS8135PHPG4 | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 Tr 10B 240MSPS Video DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
| THS8136 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 10-BIT 180-MSPS GRAPHICS AND VIDEO DAC |
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