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參數(shù)資料
| 型號： | THS8083APZPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 7/63頁 |
| 文件大?。?/td> | 320K |
| 代理商： | THS8083APZPG4 |
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32
In the case of YUV input signals, blanking levels for U and V correspond to the mid-level analog input. To handle these
signals the clamping range should be centered on the mid-level output code of the A/D.
The clamp code is 8 bits wide and spans 128 ADC output codes (a 2 LSB change to clamp code corresponds
nominally to 1 LSB change in ADC output). The programmed clamp code is independent of the PGA setting (see
later). This ensures independent brightness/clamping control.
The clamp pulse defines the timing window during which the clamp circuit is internally enabled, and is either generated
externally and supplied to the device, or it can be internally generated. In the latter case, the user can program both
the position and width of the clamp pulse with respect to the horizontal sync (HS) input.
0
255
CLIP 255
CLIP 0
+63
64
0
CLAMP CODE
ADC Output
Code Range
VIN
CLP PULSE
63
= +63 = 0
191
= 64
0
255
CLIP 255
CLIP 0
+63
64
0
CLAMP CODE
ADC Output
Code Range
VIN
CLP PULSE
63
= +63
= 0
191
= 64
Figure 32. Bottom-Level Clamping
Figure 33. Mid-Level Clamping
Influence of changing clamp codes on
A/D output, while keeping PGA gain setting
constant, in bottom-level clamp mode
Influence of changing clamp codes on
A/D output, while keeping PGA gain setting
constant, in midlevel clamp mode
3.3
Composite Sync Slicer
The THS8083A includes a circuit that compares the input signal on Ch.1, or on the dedicated CS_IN input, to a level
150 mV below the blanking level. This slicer outputs a 3-V compatible digital output on the composite sync (CS) pin.
The intended use of this circuit is for input video signals that have an embedded (negative or trilevel) sync. This is
the case for workstation-type input signals or the DTV analog interface that mandates sync-on-Y. Since the sync
amplitude is ~300 mV, the slicing level is at about 50% of the sync level. When enabled, the CS output is available
even when the device is powered down.
CS outputs the extracted composite sync. Since the PLL is prevented from updating its phase detector while the
PFD_FREEZE pin is kept high, the user asserts PFD_FREEZE during the VBI (when CS has multiple transitions per
line). This puts the PLL in free-run. While it cannot be assured with devices that have analog PLL’s, the digital PLL
in the THS8083A is assured to keep a constant output frequency and avoid frequency drift while the PLL is in free-run.
There is also no maximum on the time that PFD_FREEZE can be kept asserted to still keep a stable PLL output
frequency. In this case, the CS output can be directly connected to the THS8083A’s HS input for purposes of locking
the PLL. However, the frequency monitoring of HS, which works off signal edges, produces invalid numbers on those
lines where CS is present because of the multiple low-high transitions on these lines.
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