參數(shù)資料
型號(hào): THS5671AIDWR
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PDSO28
封裝: GREEN, PLASTIC, SOIC-28
文件頁數(shù): 10/33頁
文件大?。?/td> 1013K
代理商: THS5671AIDWR
THS5671A
14BIT, 125 MSPS, CommsDAC
DIGITALTOANALOG CONVERTER
SLAS201A DECEMBER 1999 REVISED SEPTEMBER 2002
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
reference operation
The THS5671A comprises a bandgap reference and control amplifier for biasing the full-scale output current.
The full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor
RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current
equals 32 times this bias current. The full-scale output current IOUTFS can thus be expressed as:
IOUT
FS + 32
I
BIAS +
32
V
EXTIO
R
BIAS
where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage
of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor
CEXT of 0.1 F should be connected externally to terminal EXTIO for compensation. The bandgap reference
can additionally be used for external reference operation. In that case, an external buffer with high impedance
input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference
can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may
hence be omitted. Terminal EXTIO thus serves as either input or output node.
The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing
the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the
full-scale output current range of 20 dB. The bandwidth of the internal control amplifier is defined by the internal
1 nF compensation capacitor at pin COMP1 and the external compensation capacitor C1. The relatively weak
internal control amplifier may be overridden by an externally applied amplifier with sufficient drive for the internal
1 nF load, as shown in Figure 31. This provides the user with more flexibility and higher bandwidths, which are
specifically attractive for gain control and multiplying DAC applications. Pin SLEEP should be connected to
AGND or left disconnected when an external control amplifier is used.
AVDD
1.2 V
REF
REF AMP
1 nF
+
+
AVDD
AGND
EXTLO
EXTIO
BIASJ
AVDD
IOUT1 or IOUT2
External
Control AMP
EXT Reference
Voltage
COMP1
SLEEP
Current Source Array
REXT
Internal
Control AMP
THS4041
Figure 31. Bypassing the Internal Reference and Control Amplifier
相關(guān)PDF資料
PDF描述
THS5671AIPWR PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PDSO28
THS5671AIDWG4 PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PDSO28
THS5671AIPWRG4 PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PDSO28
THS5671AIDW PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PDSO28
THS5671AIPWG4 PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PDSO28
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