參數(shù)資料
型號(hào): THS4051JG
廠商: Texas Instruments, Inc.
英文描述: 70-MHz HIGH-SPEED AMPLIFIERS
中文描述: 70 - MHz的高速放大器
文件頁(yè)數(shù): 18/30頁(yè)
文件大?。?/td> 487K
代理商: THS4051JG
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
offset voltage
The output offset voltage, (V
OO
) is the sum of the input offset voltage (V
IO
) and both input bias currents (I
IB
) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO
VIO
1
RF
RG
IIB
RS
1
RF
RG
IIB–RF
+
VI
+
RG
RS
RF
IIB–
VO
IIB+
Figure 47. Output Offset Voltage Model
optimizing unity gain response
Internal frequency compensation of the THS405x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 620
should
be used as shown in Figure 48. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
_
+
THS406x
620
Input
Output
Figure 48. Noninverting, Unity Gain Schematic
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