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參數(shù)資料
| 型號(hào)： | THS14F03IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 329K |
| 代理商： | THS14F03IPFBG4 |
THS14F01, THS14F03
14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS
WITH FIFO INTERNAL REFERENCE AND PGA
SLAS285 – JUNE 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, AVDD, DVDD
3
3.3
3.6
V
High level digital input, VIH
2
3.3
V
Low level digital input, VIL
0
0.8
V
Load capacitance, CL
5
15
pF
Clock frequency fCLK
THS14F01
0.1
1
MHz
Clock frequency, fCLK
THS14F03
0.1
3
MHz
Clock duty cycle
40%
50%
60%
Operating free air temperature
C suffix
0
25
70
°C
Operating free-air temperature
I suffix
–40
25
85
°C
electrical characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
IDDA
Analog supply current
81
90
mA
IDDD
Digital supply current
5
10
mA
Power
270
360
mW
Power down current
20
A
DC Characteristics
Resolution
14
Bits
DNL
Differential nonlinearity
±0.6
±1
LSB
INL
Integral nonlinearity
THS14F01
Best fit
±1.5
±2.5
LSB
INL
Integral nonlinearity
THS14F03
Best fit
±1.5
±2.5
LSB
Offset error
IN+ = IN–, PGA = 0 dB
0.3
%FSR
Gain error
PGA = 0 dB
1
%FSR
AC Characteristics
ENOB
Effective number of bits
11.2
11.5
Bits
THD
Total harmonic distortion
THS14F01/3
fi = 100 kHz
–81
dB
THD
Total harmonic distortion
THS14F03
fi = 1 MHz
–78
dB
SNR
Signal to noise ratio
THS14F01/3
fi = 100 kHz
72
dB
SNR
Signal-to-noise ratio
THS14F03
fi = 1 MHz
70
72
dB
SINAD
Signal to noise ratio + distortion
THS14F01/3
fi = 100 kHz
70
dB
SINAD
Signal-to-noise ratio + distortion
THS14F03
fi = 1 MHz
69
70
dB
SFDR
Spurious free dynamic range
THS14F01/3
fi = 100 kHz
80
dB
SFDR
Spurious free dynamic range
THS14F03
fi = 1 MHz
73
80
dB
Analog input bandwidth
140
MHz
FIFO trigger level = 10 samples. Performance is ensured with the output enable signal (OE) being low during no more than one rising clock edge
on CLK.
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