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參數(shù)資料
| 型號： | THS1206QDAR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | PLASTIC, TSSOP-32 |
| 文件頁數(shù)： | 40/43頁 |
| 文件大?。?/td> | 722K |
| 代理商： | THS1206QDAR |
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THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
6
TIMING SPECIFICATION OF THE SINGLE CONVERSION MODE(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc
Clock cycle of the internal clock oscillator
151
167
175
ns
1 analog input
1.5
×tc
ns
t1
Pulse width CONVST
2 analog inputs
2.5
×tc
t1
Pulse width, CONVST
3 analog inputs
3.5
×tc
4 analog inputs
4.5
×tc
tdA
Aperture time
1
ns
1 analog input
2
×tc
ns
t2
Time between consecutive start of single con-
2 analog inputs
3
×tc
ns
t2
g
version
3 analog inputs
4
×tc
ns
4 analog inputs
5
×tc
ns
1 analog input,
TL = 1
6.5
×tc + 15
ns
Delay time, DATA_AV becomes active for the
2 analog inputs, TL = 2
7.5
×tc +15
ns
y,
_
trigger level condition: TRIG0 = 0, TRIG1 = 0
3 analog inputs, TL = 3
8.5
×tc +15
ns
4 analog inputs, TL = 4
9.5
×tc +15
ns
1 analog input,
TL = 4
3
×t2 +6.5×tc+15
ns
td(DATA AV)
Delay time, DATA_AV becomes active for the
2 analog inputs, TL = 4
t2 +7.5×tc+15
ns
td(DATA_AV)
y,
_
trigger level condition: TRIG0 = 1, TRIG1 = 0
3 analog inputs, TL = 6
t2 +8.5×tc+15
ns
4 analog inputs, TL = 8
t2 +9.5×tc+15
ns
1 analog input,
TL = 8
7
×t2 +6.5×tc+15
ns
Delay time, DATA_AV becomes active for the
2 analog inputs, TL = 8
3
×t2 +7.5×tc+15
ns
y,
_
trigger level condition: TRIG0 = 0, TRIG1 = 1
3 analog inputs, TL = 9
2
×t2 +8.5×tc+15
ns
4 analog inputs, TL = 12
2
×t2 +9.5×tc+15
ns
D l
ti
DATA AV b
ti
f
th
1 analog input,
TL = 14
13
×t2 +6.5×tc+15
ns
td(DATA_AV)
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 1 TRIG1 = 1
2 analog inputs, TL = 12
5
×t2 +7.5×tc+15
ns
(
_
)
trigger level condition: TRIG0 = 1, TRIG1 = 1
3 analog inputs, TL = 12
3
×t2 +8.5×tc+15
ns
(1) Timing parameters are ensured by design but are not tested.
(2) See Figure 24.
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D0
D1
D2
D3
D4
D5
BVDD
BGND
D6
D7
D8
D9
D10/RA0
D11/RA1
CONV_CLK (CONVST)
DATA_AV
AINP
AINM
BINP
BINM
REFIN
REFOUT
REFP
REFM
AGND
AVDD
CS0
CS1
WR (R/W)
RD
DVDD
DGND
DA PACKAGE
(TOP VIEW)
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