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參數(shù)資料
| 型號： | THS1060C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位60 MSPS的IF采樣通訊模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 353K |
| 代理商： | THS1060C |
THS1060
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212 – MARCH 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AVDD
NO.
2, 5, 12
43, 45, 47
I
Analog power supply
AVSS
1, 11, 13,
41, 42, 44,
46
I
Analog ground return for internal analog circuitry
CLK+
15
I
Clock input
CLK–
16
I
Complementary clock input
D9–D0
25–34
O
Digital data output bits; LSB= D0, MSB = D9 (2s complement output format)
DRVDD
DRVSS
DVDD
DVSS
VBG
VCM
VIN+
VIN–
VREFIN–
VREFIN+
VREFOUT+
VREFOUT–
24, 37, 38
I
Digital output driver supply
23, 39, 40
I
Digital output driver ground return
17, 20, 22
I
Positive digital supply
18, 19, 21
I
Digital ground return
Band gap reference. Bypass to ground with a 1
μ
F and a 0.01
μ
F chip capacitor.
Common mode voltage output. Bypass to ground with a 0.1
μ
F and a 0.01
μ
F chip device capacitor.
Analog signal input
10
O
48
O
3
I
4
I
Complementary analog signal input
7
I
External reference input low
8
I
External reference input high
Internal reference output. Compensate with a 1
μ
F and a 0.01
μ
F chip capacitor.
Internal reference output. Compensate with a 1
μ
F and a 0.01
μ
F chip capacitor.
9
O
6
O
detailed description
The THS1060 uses a differential pipeline architecture and assures no missing codes over the full operating
temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible
bandwidth. The differential analog inputs are terminated with a 900
resistor. The inputs are then fed to a unity
gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor op-amp based
circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional block diagram.
The digital output of the 10 stages and the last 1 bit flash are sent to a digital correction logic block which then
outputs the final 10 bits.
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