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參數(shù)資料
| 型號： | THS1050I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位50 MSPS的IF采樣通訊模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 397K |
| 代理商： | THS1050I |
THS1050
10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS278 – APRIL 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
Digital Error Correction
S/H
Stage 1
Stage 10
Reference
2.0 V
3.0 V
AVDD/2
Timing
VIN–
VREFOUT+
VCM
CLK+
DVSS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AVDDDVDD
D/A
Σ
A/D
Σ
D/A
A/D
A/D
VREFOUT–
VREFIN–
VREFIN+
CLK–
1
1
1
Buffer
DRVDD
AVSS
DRVSS
Stages 2 – 9
VIN+
900
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AVDD
NO.
2, 5, 12 43,
45, 47
I
Analog power supply
AVSS
1, 11, 13, 41,
42, 44, 46
I
Analog ground return for internal analog circuitry
CLK+
15
I
Clock input
CLK–
16
I
Complementary clock input
D9–D0
25–34
O
Digital data output bits; LSB= D0, MSB = D9 (2s complement output format)
DRVDD
DRVSS
DVDD
DVSS
VBG
VCM
VIN+
VIN–
VREFIN–
VREFIN+
VREFOUT+
VREFOUT–
24, 37, 38
I
Digital output driver supply
23, 39, 40
I
Digital output driver ground return
17, 20, 22
I
Positive digital supply
18, 19, 21
I
Digital ground return
Band gap reference. Bypass to ground with a 1
μ
F and a 0.01
μ
F chip capacitor.
Common mode voltage output. Bypass to ground with a 0.1
μ
F and a 0.01
μ
F chip device capacitor.
Analog signal input
10
O
48
O
3
I
4
I
Complementary analog signal input
7
I
External reference input low
8
I
External reference input high
Internal reference output. Compensate with a 1
μ
F and a 0.01
μ
F chip capacitor.
Internal reference output. Compensate with a 1
μ
F and a 0.01
μ
F chip capacitor.
9
O
6
O
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