參數(shù)資料
型號: THS1040IDWR
廠商: Texas Instruments, Inc.
元件分類: ADC
英文描述: 3-V, 10-BIT , 40-MSPS CMOS ANALOG TO DIGITAL CONVERTER
中文描述: 3伏,10位,40 MSPS的CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 6/32頁
文件大?。?/td> 545K
代理商: THS1040IDWR
SLAS290C OCTOBER 2001 REVISED OCTOBER 2004
6
www.ti.com
electrical characteristics
over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, fs = 40 MSPS/50% duty cycle, MODE = AVDD (internal reference),
differential input range = 1 VPP and 2 VPP, TA = Tmin to Tmax (unless otherwise noted) (continued)
dynamic performance (ADC)
PARAMETER
TEST CONDITIONS
f = 4.8 MHz, 0.5 dBFS
MIN
8.8
TYP
9.6
MAX
UNIT
ENOB
Effective number of bits
Bits
f = 20 MHz, 0.5 dBFS
9.5
SFDR
Spurious free dynamic range
f = 4.8 MHz, 0.5 dBFS
60.5
72
dB
f = 20 MHz, 0.5 dBFS
70
THD
Total harmonic distortion
f = 4.8 MHz, 0.5 dBFS
72.5
61.3
dB
f = 20 MHz, 0.5 dBFS
71.6
SNR
Signal-to-noise ratio
f = 4.8 MHz, 0.5 dBFS
55.7
60
dB
f = 20 MHz, 0.5 dBFS
57
SINAD
Signal-to-noise and distortion
f = 4.8 MHz, 0.5 dBFS
55.6
59.7
dB
f = 20 MHz, 0.5 dBFS
59.6
BW
Full power bandwidth (3 dB)
900
MHz
digital specifications
PARAMETER
MIN
NOM
MAX
UNIT
Digital Inputs
VIH
High-level input voltage
Clock input
0.8
×
AVDD
0.8
×
DVDD
V
All other inputs
VIL
Low-level input voltage
Clock input
0.2
×
AVDD
0.2
×
DVDD
V
All other inputs
IIH
IIL
Ci
Digital Outputs
High-level input current
1
μ
A
μ
A
pF
Low-level input current
|1|
Input capacitance
5
VOH
VOL
High-level output voltage
Iload = 50
μ
A
Iload = 50
μ
A
DVDD0.4
V
Low-level output voltage
0.4
V
High-impedance output current
±
1
μ
A
Rise/fall time
Cload = 15 pF
3.5
ns
Clock Input
tc
tw(CKH)
tw(CKL)
Clock cycle time
25
200
ns
Pulse duration, clock high
11.25
110
ns
Pulse duration, clock low
11.25
110
ns
Clock duty cycle
45%
50%
55%
td(o)
Clock to data valid, delay time
9.5
16
ns
Pipeline latency
4
Cycles
td(AP)
Aperture delay time
0.1
ns
Aperture uncertainty (jitter)
1
ps
timing
PARAMETER
MIN
TYP
MAX
UNIT
td(DZ)
td(DEN)
VO(BIASREF)
Output disable to Hi-Z output, delay time
0
10
ns
Output enable to output valid, delay time
0
10
ns
Output voltage
MODE = AVDD
(AVDD/2) 0.1
(AVDD/2) + 0.1
V
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