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參數(shù)資料
| 型號： | TFP513 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TI PANELBUS DIGITAL TRANSMITTER |
| 中文描述： | 德州儀器PANELBUS數(shù)字發(fā)射機 |
| 文件頁數(shù)： | 15/29頁 |
| 文件大小： | 424K |
| 代理商： | TFP513 |
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SLLS611 AUGUST 2004
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
data de-skew feature
The de-skew feature allows adjustment of the input setup/hold time. Specifically, the input data DATA[23:0] can
be latched slightly before or after the latching edge of the clock IDCK
±
depending on the amount of de-skew
desired. When de-skew enable (DKEN) is enabled, the amount of de-skew is programmable by setting the three
bits DK[3:1]. When disabled, a default de-skew setting is used. DKEN and DK[3:1] are accessed through
registers only when I
2
C is enabled.
The input setup/hold time (see Figure 8) can be varied with respect to the input clock by an amount t
CD
given
by the formula:
t
(CD)
= (DK[3:1] – 4)
×
t
(STEP)
where:
t
(STEP)
is the adjustment increment amount
DK[3:1] is a number from 0 to 7 represented as a 3-bit binary number
t
(CD)
is the cumulative de-skew amount
(DK[3:1]-4) is simply a multiplier in the range {-4,-3,-2,-1, 0, 1, 2, 3} for t
(STEP)
. Therefore, data can be latched
in increments from 4 times the value of t
(STEP)
before the latching edge of the clock to 3 times the value of t
(STEP)
after the latching edge. Note that the input clock is not changed, only the time when data is latched with respect
to the clock.
t(CD)
000
4
×
t(STEP)
100
0
Default Falling
111
3
×
t(STEP)
000
4
×
t(STEP)
100
0
Default Rising
111
3
×
t(STEP)
DATA[23:0]
IDCK
±
DK[3:1]
t(CD)
t(CD)
t(CD)
t(CD)
Figure 8. De-Skew Function Timing Diagram
hot plug/unplug (auto connect/disconnect detection)
The TFP513 supports hot plug/unplug (auto connect/disconnect detection) for the DVI link. The receiver sense
input (RSEN) bit indicates if a DVI receiver is connected to TXC+ and TXC. The HTPLG bit reflects the current
state of the HTPLG pin connected to the monitor via the DVI connector. When I
2
C is disabled (ISEL = 0), the
RSEN value is available on the MSEN pin. When I
2
C is enabled, the connection status of the DVI link and
HTPLG sense pins is provided by the CTL_2_MODE register. The MSEL bits of the CTL_2_MODE register can
program the MSEN to output the HTPLG value, the RSEN value, an interrupt, or be disabled.
The source of the interrupt event is selected by TSEL in the CTL_2_MODE register. An interrupt is generated
by a change in status of the selected signal. The interrupt status is indicated in the MDI bit of CTL_2_MODE
and can be output on the MSEN pin. The interrupt continues to be asserted until a 1 is written to the MDI bit,
resetting the bit back to 1. Writing 0 to the MDI bit has no effect.
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