參數(shù)資料
型號: TFDU6108-TR3
廠商: Vishay Intertechnology,Inc.
英文描述: Fast Infrared Transceiver Module (4 Mbit/s), IrDA Serial Interface Compatible, 2.7 V to 5.5 V Supply Voltage Range
中文描述: 快速紅外收發(fā)器模塊(4兆位/秒),紅外串行接口兼容,2.7 V至5.5 V電源電壓范圍
文件頁數(shù): 16/27頁
文件大小: 940K
代理商: TFDU6108-TR3
www.vishay.com
16
Document Number 82537
Rev. 1.6, 25-Jun-04
VISHAY
TFDU6108
Vishay Semiconductors
Data Acknowledgement
Data acknowledgement generated by the slave is
available if the APEN bit is set to 1 in the common
control register. In IrDA default state this functionality
is disabled. In default state of the TFDU6108 it is
enabled (see above). It is strongly recommended that
this functionality is enabled to be on the safe side for
correct data transmission during SITC mode.
Registers Data Depth
In general the whole data registers consist of a data
depth of eight bits. But sometimes it is unnecessary to
implement the full depth. In such a case the invisible
bits consider like a zero.
Used Index Commands
The table shows the valid index commands, its allowable modes, and the data depth to them.
Commands
INDEX [3:0]
0h
W/R
1h
W/R
2h
W/R
Bh - 3h
X
Ch
X
Dh
W
Main-ctrl-0 register values
1)
APEN - Acknowledge Pulse Enable, (optional)
This bit is used to enable the acknowledge pulse. When it is set to 1 and RX OEN is 1 (receiver output enabled) the IRRX/SRDAT line will
be pulsed low for one clock cycle upon successful completion of every write command or special command with individual (non broadcast)
transceiver address. The internal signal from the receiver photo diode is disconnected
when this bit is set to 1.
Mode
Action
Register Name
Data
Bits
[4.2:0]
[3:0]
[7:4]
Default Value
TFDU6108
14h
00h
70h
Common control
Infrared mode
Txd power level
Not used
Not used
Reset transceiver,
Only one byte!
Not used
Not used
Not used
Extended indexing
main-ctrl-0 register
main-ctrl-1 register
main-ctrl-2 register
R
X
W
R
Eh
Fh
Value
bit 0
Function
Default
active (!)
PM SL - Power Mode Select
0
low power mode (sleep mode)
1
normal operation power mode
RX OEN - Receiver Output Enable
0
IRRX/SRDAT line disable (tri-stated)
1
IRRX/SRDAT line enabled
TLED EN - Transmitter LED Enable
0
disabled
1
enabled
not used
APEN
1)
bit 1
active
bit 2
active
bit 3
bit 4
not used
enabled
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