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參數(shù)資料
| 型號： | TFDU5107-TT3 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Integrated Low Profile Transceiver Module for Telecom Applications |
| 中文描述： | 超薄集成收發(fā)模塊的電信應(yīng)用 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 233K |
| 代理商： | TFDU5107-TT3 |
TFDU5107
Vishay Semiconductors
Rev. A1.4, 01-Nov-02
7 (13)
www.vishay.com
Document Number 82534
Recommended SMD Pad Layout
The leads of the device should be soldered in the center position of the pads.
7 x 1 = 7
8
1
1
16524
2.5 (
≥
2.0)
0.6 (
≤
0.7)
Figure 3. TFDU5107 Baby Face (Universal)
Recommended Solder Profile
Time ( s )
T
14874
°
0
30
60
90
120
150
180
210
240
0
50
100
150
200
250
300
350
2 - 4
°
C/s
10 s max.
@ 230
°
C
90 s max.
120 - 180 s
2 - 4
°
C/s
Figure 4. Recommended Solder Profile
Current Derating Diagram
0
100
200
300
400
500
600
–40 –20
0
20
Temperature (
°
C )
40
60
80 100 120 140
P
14875
Current derating as a function of
the maximum forward current of
IRED. Maximum duty cycle: 25%.
Figure 5. Current Derating Diagram
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