參數(shù)資料
型號: TEA6822T-T
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: AM/FM, AUDIO SINGLE CHIP RECEIVER, PDSO56
封裝: PLASTIC, SOT-190-1, VSOP-56
文件頁數(shù): 44/48頁
文件大?。?/td> 351K
代理商: TEA6822T-T
1997 Feb 12
5
Philips Semiconductors
Preliminary specication
In Car Entertainment (ICE) car radio
TEA6820T; TEA6822T
PINNING
SYMBOL
PIN
DESCRIPTION
QDET1
1
demodulator tank 1
QDET2
2
demodulator tank 2
TSWITCH
3
time switch input
AGND
4
analog ground
VDDA1
5
analog supply voltage 1 (+5 V)
HFBUS1
6
HF bus 1 output;
pull-up to +5 V
HFBUS2
7
HF bus 2 output;
pull-up to +5 V
XTAL1
8
crystal oscillator 1
XTAL2
9
crystal oscillator 2
fref(p)
10
PLL reference frequency
output (p)
fref(n)
11
PLL reference frequency
output (n)
Iref
12
reference current
FMIF1IN1
13
72 MHz FM-IF input 1
FMIF1IN2
14
72 MHz FM-IF input 2
TSDR
15
time constant for SDR
TSDS
16
time constant for SDS
VSDS
17
SDS control voltage input
VSDR
18
SDR control voltage input
FMIF2OUT1
19
FM mixer output 1
FMIF2OUT2
20
FM mixer output 2
Vref
21
reference voltage output
AMIF2OUT1
22
AM mixer output 1
AMIF2OUT2
23
AM mixer output 2
FMAMDEC
24
FM/AM 10.7 MHz decoupling
PHASEDET
25
phase detector output
PILDET
26
pilot detector output
FMAM10.7
27
FM/AM 10.7 MHz input
VDDA2
28
analog supply voltage 2
FMIFAMPOUT
29
FM-IF amplier output
AFGND
30
AF ground
DEEMPHR
31
de-emphasis capacitor right
DEEMPHL
32
de-emphasis capacitor left
AMIF2IN1
33
AM-IF2 input 1
AMIF2IN2
34
AM-IF2 input 2
FMIN2
35
FM limiter input
DCFEED
36
DC feed FM limiter
FMIN1
37
FM limiter input
LEVELADJ
38
level adjustment input
CAFC
39
AFC capacitor
MPBUF
40
multi-path buffer time constant
OUTLEFT
41
AF output left
FMSTOP
42
FMSTOP adjustment input
RDS/AMSTOP
43
MPX for RDS/AMSTOP
adjustment input
OUTRIGHT
44
AF output right
MPXIN
45
stereo decoder MPX input
i.c.
46
internally connected
MPXOUT
47
FM demodulator MPX output
AMAFOUT
48
AM demodulator AF output
Vmute/AML
49
mute voltage/AM level
LEVELUNWEIG
50
unweighted level output
IACCONTR
51
IAC control voltage
VDDD
52
digital supply voltage
SDA
53
serial data input/output;
pull-up to +5 V
SCL
54
serial clock input;
pull-up to +5 V
DGND
55
digital ground
VDDA3
56
analog supply voltage 3
(+8.5 V)
SYMBOL
PIN
DESCRIPTION
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