參數(shù)資料
型號: TEA5777HN/N2,518
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: AM/FM, AUDIO SINGLE CHIP RECEIVER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-1, HVQFN-48
文件頁數(shù): 24/47頁
文件大?。?/td> 219K
代理商: TEA5777HN/N2,518
TEA5777_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 11 April 2006
30 of 47
Philips Semiconductors
TEA5777
Low-power AM/FM stereo radio for handheld applications
Table 41.
Digital input and output characteristics
VCCA =VCCD = 3 V; Tamb =25 °C; unless otherwise specied.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Software programmable ports: pins SWPORT1 and SWPORT2
VOH
HIGH-level output voltage
IO = 0 A
-
2.4
-
V
VOL
LOW-level output voltage
IO =1mA
on pin SWPORT1
-
109.7
-
mV
on pin SWPORT2
-
105.5
-
mV
Io(source) output source current
VO =0 V
6
9
14
mA
Io(sink)
output sink current
VO =3 V
6
9
14
mA
VO = 0.8 V; Rpu =1k
on pin SWPORT1
-
7.85
-
mA
on pin SWPORT2
-
8.04
-
mA
Digital inputs
VIH
HIGH-level input voltage
0.45VCCD
--
V
VIL
LOW-level input voltage
-
0.2VCCD
V
Digital outputs: pins CLOCK, DATA and WRITE_READ
VOL
LOW-level output voltage
IOL = 500 A; open-collector
-
450
mV
IOL
LOW-level output current
open-collector
500
-
A
Table 42.
Bus timing characteristics
VCCA =VCCD = 3 V; Tamb =25 °C; unless otherwise specied.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Timing I2C-bus
fSCL
SCL clock frequency
-
400
kHz
tHIGH
HIGH period of the SCL clock
1
-
s
tLOW
LOW period of the SCL clock
1
-
s
Timing 3-wire bus; see Figure 7 and Figure 8
fi(clk)
clock input frequency
-
1
MHz
tclk(H)
clock HIGH time
300
-
ns
tclk(L)
clock LOW time
300
-
ns
Write mode
tw(W)
write enable pulse width
1
-
s
tsu(clk)
clock setup time
300
-
ns
tsu(D)
data input set-up time
in write mode
100
-
ns
th(D)
data input hold time
in write mode
100
-
ns
Read mode
tw(R)
read enable pulse width
1
-
s
tsu(clk)
clock setup time
300
-
ns
th(Q)
data output hold time
in read mode
10
-
ns
td(Q)
data output delay time
in read mode
-
100
ns
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