參數(shù)資料
型號(hào)： TEA5766UK/N1/S21,1
廠商： NXP SEMICONDUCTORS
元件分類： 接收器
英文描述： FM, AUDIO SINGLE CHIP RECEIVER, PBGA25
封裝： 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25
文件頁數(shù)： 30/59頁
文件大?。?/td> 273K
代理商： TEA5766UK/N1/S21,1
TEA5766UK_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 22 March 2007
36 of 59
NXP Semiconductors
TEA5766UK
Stereo FM radio + RDS
11. Registers
11.1 Register map
The reference for the register map is the Motorola SPI addressing. The actual register is in
fact one long register, so the I2C-bus bytes are mapped onto the SPI registers.
[1]
Table 13 shows how the I2C-bus bytes are mapped onto the SPI bytes.
[2]
First four bits are the version bits and change with every mask set.
11.2 Register description
Table 12.
Register overview
Register name SPI address
I2C-bus byte number
R/W access
Reset
Reference
Read
Write
INTREG
02
0R - 1R
0W[1]
R/W
0000h
FRQSET
03
2R - 3R
1W - 2W
R/W
8000h
TNCTRL
04
4R - 5R
3W - 4W
R/W
08D2h
FRQCHK
05
6R - 7R
R
-
TUNCHK
06
8R - 9R
R
-
TESTREG
07
10R - 11R
5W - 6W
R/W
0000h
RDSR1
08
12R - 13R
R
-
RDSR2
09
14R - 15R
R
-
RDSR3
10
16R - 17R
R
-
RDSR4
11
18R - 19R
R
-
RDSW1
12
20R - 21R
7W - 8W
R/W
0010h
RDSW2
13
22R - 23R
9W - 10W
R/W
0000h
MANID
00
24R - 25R
R
CHIPID
01
26R - 27R
R
5766h
Table 13.
SPI to I2C-bus map for SPI address 02
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPI
02
I2C
0R
1R/0W
Table 14.
INTREG - SPI address 02 or I2C byte 0R + byte 1R/byte 0W bit description
Bit
Symbol
Access
Reset
value
Description
SPI
I2C
15
7
DAVFLG
R
0
1 = RDS data is available
14
6
TESTBIT
R
0
internal use
13
5
LSYNCFL
R
0
1 = synchronization is lost
12
4
IFFLAG
R
0
1 = IF count is not correct
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