參數(shù)資料
型號(hào)： TEA1081
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Supply circuit with power-down for telephone set peripherals
中文描述： SPECIALTY TELECOM CIRCUIT, PDIP8
封裝： 0.300 INCH, PLASTIC, SOT-97, DIP-8
文件頁(yè)數(shù)： 4/16頁(yè)
文件大?。?/td> 77K
代理商： TEA1081
September 1994
4
Philips Semiconductors
Product specification
Supply circuit with power-down for
telephone set peripherals
TEA1081
FUNCTIONAL DESCRIPTION
The TEA1081 is a supply interface between telephone line
and peripheral devices in the telephone set. The high input
impedance of the circuit allows direct connection to the
telephone line (via a diode bridge). An inductor function is
obtained by amplifier A1, resistor R
S
(see Fig.1) and an
external low-pass RC filter.
Under the control of amplifier A2, transistor TR1 supplies
peripheral devices and transistor TR2 minimizes line
signal distortion by momentarily diverting input current to
ground whenever the instantaneous value of the line
voltage drops below the output voltage.
Internal circuits are biased by a temperature and line
voltage compensated reference current source.
The power-down circuit isolates the supply circuit from
external circuitry.
Line terminals: LN and VN (pins 1 and 2)
The input terminals LN and VN can be connected directly
to the line. The minimum DC line voltage required at the
input is expressed by formula (1); see also Table 1.
V
LN
I
1
R
S
V
LNmin
+
=
(1)
Table 1
Explanation of formula (1).
The internal current (I
INT
) at I
O
= 0 mA is typically 0.8 mA
at V
LN
= 4 V and reaches a maximum of 1.4 mA at
V
LN
= 12 V.
Supply terminals: QS and VA (pins 7 and 6)
Peripheral devices are supplied from QS (pin 7). Two
modes of output voltage regulation are available.
O
UTPUT VOLTAGE FOLLOWS LINE VOLTAGE
(
SEE FIG
.3)
The TEA1081 operates in this mode when there is no
external resistor (R
V
) between QS and VA (see Fig.6).
SYMBOL
DESCRIPTION
I
1
R
S
V
LNmin
input current
internal series resistance
minimum instantaneous line voltage
(1.4 V at I
O
= 5 mA)
required peak level of AC line voltage
V
LN(P)
×
V
LN P
V
( )
+
The output voltage follows the line voltage and is
expressed by formula (2); see also Table 2.
V
O
V
LN
–
=
(2)
Table 2
Explanation of formula (2).
R
EGULATED OUTPUT VOLTAGE
(
SEE FIG
.4)
The circuit operates in this mode when an external resistor
(R
V
) is connected between QS and VA (see Fig.6).
The output voltage is held constant at V
O
= 2
×
I
6
×
R
V
(V)
as soon as the line voltage
V
LN
> (2
×
I
6
×
R
V
+ I
1
×
R
S
+ 0.5) (V)
The control current I6 is typically 20
μ
A.
SYMBOL
DESCRIPTION
V
LN
I
1
R
S
line voltage
input current
internal series resistance
I
1
R
S
0.5
+
×
(
)
V
( )
Fig.3 Output voltage as a function of line voltage.
Application without R
V
.
(1) I
1
= 5 mA.
(2) I
1
= 20 mA.
(3) I
1
= 30 mA; not valid for TEA1081T.
handbook, halfpage
VO
(V)
0
10
0
2
MLC168
4
6
8
2
4
6
8
VLN
(1)
(2)
(3)
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