參數(shù)資料
型號(hào): TEA1069N
廠商: NXP SEMICONDUCTORS
元件分類: 無繩電話/電話
英文描述: Versatile speech/dialler/ringer with music-on-hold
中文描述: TELEPHONE MULTIFUNCTION CKT, PDIP42
封裝: SHRINK, PLASTIC, DIP-42
文件頁數(shù): 15/44頁
文件大?。?/td> 301K
代理商: TEA1069N
1998 Jan 08
15
Philips Semiconductors
Product specification
Versatile speech/dialler/ringer with
music-on-hold
TEA1069; TEA1069A
Fig.12 Ringer frequency detection.
handbook, full pagewidth
CE/FDI
TONE
MBH200
VDD
VEE
sample
time
ringer response delay
(
<
1.5 frequency cycle)
sync
time
In case of a valid ringer signal the user is alerted through
a melody at the TONE output, generated by the ringer part
of the TEA1069 and TEA1069A. This melody follows the
cadence of the ringer signal. Both the melody and the
volume can be selected. The melody frequency and
duration are given in Table 2.
Table 2
Ringer melodies
C
RADLE SWITCH INPUT
:
PIN
CSI
To distinguish among different operating states after
CE/FDI is activated, input CSI is used. The basic states
are shown in Table 3.
Table 3
TEA1069 and TEA1069A basic states
NAME
FREQUENCY (Hz)
DURATION (ms)
Bell 1
Bell 2
Bell 3
Bell 4
800 + 1066 + 1333
826 + 925 + 1027
1037 + 1161 + 1297 28 + 28 + 28
1297 + 1455 + 1621 28 + 28 + 28
28 + 28 + 28
28 + 28 + 28
INPUT CSI
INPUT CE/FDI
STATE
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
standby
not applicable
ringer
on-line
For the hands-free state refer to Fig.23.
P
ULSE DIALLER
:
PINS
DP/FL, MOH/DMO
AND
MUTE
The pulse dialling system uses line current interruptions to
signal the digits dialled to the exchange. The number of
line current interruptions corresponds with the digit dialled
except for the digit [0] which is characterized by
10 interruptions. Before each digit there is an inter-digit
pause.
Valid keys are the digits [0] to [9] and [PAUSE].
The pulse dialling mode, the make/break ratio and the
access pause time depend on the diode options: PTS,
M/B, APT and APT2. DP/FL is LOW when V
DD
is below
power-on reset trip level and when RESET is HIGH.
The MOH/DMO pin (diode GOS =
on
) is used to reduce
the voltage swing over the a/b terminals during pulse
dialling. Several countries require this feature. The MUTE
pin is an open drain output which requires a pull-up
resistor. MUTE is HIGH when V
DD
is below power-on reset
trip level and when RESET is HIGH.
Figure 13 shows the timing diagram in pulse dialling mode
when keys [3], [RECALL] and [4] are pressed.
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