參數(shù)資料
型號: TE28F200BX-B80
廠商: INTEL CORP
元件分類: DRAM
英文描述: 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
中文描述: 128K X 16 FLASH 12V PROM, 80 ns, PDSO56
封裝: 20 X 14 MM, TSOP-56
文件頁數(shù): 39/55頁
文件大小: 638K
代理商: TE28F200BX-B80
E
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
Characteristicsduring read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
3. Refer to command definition table for valid A
IN
. (Table 7)
4. Refer to command definition table for valid D
IN
. (Table 7)
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at V
HH
or WP# should be held at V
IH
until operation completes
successfully.
7. Time t
PHBR
is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. See Test Configuration(Figure 14), 3.3 V Standard Test component values.
10. See Test Configuration(Figure 14), 5 V High-Speed Test component values.
11. See Test Configuration(Figure 14), 5 V Standard Test component values.
2-MBIT SmartVoltage BOOT BLOCK FAMILY
39
SEE NEW DESIGN RECOMMENDATIONS
ADDRESSES (A)
CE# (E)
OE# (G)
WE# (W)
DATA (D/Q)
RP# (P)
IH
V
IL
V
V
IH
IL
V
V
IH
IL
V
IH
V
IL
V
HH
V
V
6.5V
IL
V
IL
V
IN
D
IN
A
IN
A
WHEH
t
WHWL
t
Valid
SRD
IN
D
WHQV1,2,3,4
t
PHHWH
t
IH
PHWL
t
High Z
WHDX
t
IH
V
IL
V
V (V)
1
2
3
4
6
5
PPH
V
V
PPLK
V
PPH
1
2
WP#
IL
V
IH
V
AVAV
t
AVWH
t
WHAX
t
DVWH
t
WLWH
t
QVPH
t
QVVL
t
VPWH
t
IN
D
ELWL
t
NOTES:
1. V
CC
Power-Up and Standby.
2. Write program or Erase Set-Up Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data.
6. Write Read Array Command.
0530_17
Figure 17. AC Waveforms for Write Operations (WE#
–Controlled Writes)
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