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參數(shù)資料
| 型號： | TDK-73M2901CL |
| 廠商： | TDK Corporation |
| 英文描述： | V.22 BIS SINGLE CHIP MODEM |
| 中文描述： | .22結(jié)算單芯片調(diào)制解調(diào)器 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 282K |
| 代理商： | TDK-73M2901CL |
73M2901CL
V.22bis Single Chip Modem
SPECIFYING A CRYSTAL
3
The manufacturer of a crystal resonator verifies its
frequency of oscillation in a test set-up, but to
ensure that the same frequency is obtained in the
application, the circuit conditions must be the same.
The TDK 73M2901CL modem requires a parallel
mode
(anti-resonant)
specifications of which are as follows:
Mode:
Frequency:
Frequency tolerance:
±50 ppm at initial temperature.
Temperature drift:
An additional ±50 ppm over full range.
Load capacitance:
ESR:
crystal,
the
important
Parallel (anti-resonant)
11.0592 MHz
18pF or 20pF
75
max.
Less than 1mW.
Drive level:
The peak voltage level of the oscillator should be
checked to assure it will not violate the maximum
voltage levels allowed on the oscillator pins. A
resistor in series with the crystal can be used, if
necessary, to reduce the oscillator
’
s peak voltage
levels.
PIN DESCRIPTIONS
Crystals with low ESRs may oscillate at higher than
specified voltage levels.
RESET
A reset is accomplished by holding the RESET pin
high. To ensure a proper power-on reset, the reset
pin must be held high for a minimum of 3
μ
s. At
power on, the voltage at VPD, VPA, and RESET
must come up at the same time for a proper reset.
The signals
,
and
for 25ms, acknowledging the reset operation, within
a 250ms time window after the reset-triggering
event. The 73M2901CL is ready for operation after
that 250ms window and/or after the signals
and
become active.
will be held inactive
,
ASYNCHRONOUS AND SYNCHRONOUS SERIAL
DATA INTERFACE
The serial data interface consists of the TXD and
RXD data paths (LSB shifted in and out first,
respectively); and the TXCLK and RXCLK serial
clock outputs associated with the data pins;
/
flow control;
synchronous mode, the data is passed at the bit rate
(tolerance is +1%, -2.5%).
,
and
. In
POWER PIN DESCRIPTION
PIN
NAME
PLCC
VPA
VNA
VPD
6, 25, 29
VND
5, 22, 26
32 pin
32 pin
TQFP
10
16
2, 20, 25
1, 17, 22
44 pin LQFP
TYPE
DESCRIPTION
15
21
16
22
I
I
I
I
Positive analog voltage (Analog supply)
Negative analog voltage (Analog ground)
Positive digital voltage (Digital supply)
Negative digital voltage (Digital ground)
2, 12, 27, 33
11, 24, 44, 28
ANALOG INTERFACE PIN DESCRIPTION
PIN
NAME
PLCC
RXA
20
TXAN
16
TXAP
17
32 pin
32 pin
TQFP
15
11
12
44 pin LQFP
TYPE
DESCRIPTION
21
17
18
I
O
O
Receive Analog input
Transmit Analog - output
Transmit Analog + output
Analog Band Gap voltage reference (0.1
μ
F to
VNA). This pin must not be connected to external
circuitry other than the decoupling capacitor.
Analog reference voltage (0.1
μ
F to VNA)
VBG
19
14
20
O
VREF
18
13
19
O
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