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參數(shù)資料
| 型號： | TDIH |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC1800 Series of In-System Programmable Configuration PROMs |
| 中文描述： | XC1800系列在系統(tǒng)可編程配置PROM的 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 117K |
| 代理商： | TDIH |
R
XC1800 Series of In-System Programmable Configuration PROMs
2
September 17, 1999 (Version 1.3)
Pinout and Pin Description
Table 1: Pin Names and Descriptions
Pin
Name
Boundary
Scan
Order
Function
Pin Description
44-pin
VQFP
44-pin
PLCC
20-pin
SOIC & PLCC
D0
4
DATA OUT D0 is the DATA output pin to provide data
for configuring an FPGA in serial mode.
OUTPUT
ENABLE
40
2
1
3
D1
6
DATA OUT D0- D7 are the output pins to provide par-
allel data for configuring a Xilinx FPGA in
express mode.
ENABLE
29
35
16
5
OUTPUT
D2
2
DATA OUT
42
4
2
1
OUTPUT
ENABLE
D3
8
DATA OUT
27
33
15
7
OUTPUT
ENABLE
D4
24
DATA OUT
9
15
7*
23
OUTPUT
ENABLE
D5
10
DATA OUT
25
31
14
9
OUTPUT
ENABLE
D6
17
DATA OUT
14
20
9
16
OUTPUT
ENABLE
D7
14
DATA OUT
19
25
12
13
OUTPUT
ENABLE
CLK
0
DATA IN
Each rising edge on the CLK input incre-
ments the internal address counter if both
CE is low and OE/RESET is high.
43
5
3
OE/
RESET
20
DATA IN
When Low, this input holds the address
counter reset and the DATA output at
high impedance.
13
19
8
19
DATA OUT
18
OUTPUT
ENABLE
CE
15
DATA IN
When CE is High, this pin puts the device
into standby mode. The DATA output pin
is at High impedance, and the device is in
low power standby mode.
15
21
10
CF
22
DATA OUT Allows JTAG CONFIG instruction to ini-
tiate FPGA configuration without power-
ing down FPGA.
10
16
7*
21
DATA IN
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