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參數(shù)資料
| 型號： | TDIH |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC1800 Series of In-System Programmable Configuration PROMs |
| 中文描述： | XC1800系列在系統(tǒng)可編程配置PROM的 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 117K |
| 代理商： | TDIH |
R
XC1800 Series of In-System Programmable Configuration PROMs
10
September 17, 1999 (Version 1.3)
Figure 5: (a) Master Serial Mode (b) Virtex Select MAP Mode (c) Spartan XL Express Mode
PROGRAM
DIN
CCLK
INIT
DONE
FIRST
PROM
DATA
CEO
CLK
CE
OE/RESET
CF
OPTIONAL
Slave FPGAs
with Identical
Configurations
Vcc
FPGA
(Low Resets the Address Pointer)
Vcc
VCCO
Cascaded
PROM
DATA
CLK
CE
OE/RESET
OPTIONAL
Daisy-chained
FPGAs with
Different
Configurations
D
OUT
MODES
Vcco
M0
M1
M2
PROGRAM
VIRTEX
Select MAP
BUSY
CS
WRITE
INIT
D0-D7
CCLK
DONE
3.3V
VCC
XC18xx
VCCO
CLK
Virtex Select MAP Mode
D0-D7
CE
OE/RESET
NC
CF
3.3V
External Osc
Vcc
Vcco
CEO
4.7K
4.7k
I/O*
M0
M1
CS1
PROGRAM
Spartan XL
DOUT
DONE
INIT
XC18xx
CEO
CE
OE/RESET
CLK
Spartan XL Express Mode
Master Serial Mode
8
CF
VCC
VCCO
Vcc
Vcco
D0-D7
D0-D7
Vcc
CCLK
M0
M1
CS1
PROGRAM
Optional
Daisy-Chained
Spartan XL
DOUT
DONE
INIT
D0-D7
CCLK
Vcc
4k
8
To Additional
Optional
Daisy-Chained
Devices
To Additional
Optional
Daisy-Chained
Devices
CCLK
I/O*
4.7k
*CS and WRITE must be pulled down to be used as I/O. One option is shown.
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