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參數(shù)資料
| 型號： | TDC1147 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 7-Bit, 15 Msps Monolithic Video A/D Converter(7位,15Msps 單片視頻A/D轉(zhuǎn)換器) |
| 中文描述： | 7位，15 Msps的單片視頻A / D轉(zhuǎn)換（7位，15Msps單片視頻的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 75K |
| 代理商： | TDC1147 |
TDC1147
PRODUCT SPECIFICATION
2
1
2
3
4
5
6
7
8
9
10
11
12
V
IN
R
T
A
GND
D
GND
NMINV
(MSB) D
1
D
2
D
3
D
4
V
CC
V
EE
A
GND
24
23
22
21
20
19
18
17
16
15
14
13
V
IN
R
B
A
GND
D
GND
CONV
D
7
(LSB)
D
6
D
5
V
CC
NLINV
V
EE
A
GND
24 Lead Ceramic DIP
65-1147-02
Functional Description
General Information
The TDC1147 has two functional sections: a comparator
array and encoding logic. The comparator array compares
the input signal with 127 reference voltages to produce an
N-of-127 code (sometimes referred to as a “thermometer”
code, as all the comparators referred to voltages more posi-
tive than the input signal will be off, and those referred to
voltages more negative than the input signal will be on).
The encoding logic converts the N-of-127 code into binary
or offset two’s complement coding, and can invert either
output code. This coding function is controlled by DC
signals on pins NMINV and NLINV.
Power
The TDC1147 operates from two supply voltages, +5.0V
and -5.2V. The return path for I
the +5.0V supply) is D
GND
. The return path for I
current drawn from the -5.2V supply) is A
and ground pins must be connected.
CC
(the current drawn from
EE
(the
GND
. All power
Reference
The TDC1147 converts analog signals in the range
V
RB
￡
V
IN
￡
V
RT
into digital form. V
applied to the pin at the bottom of the reference resistor
chain) and V
RT
(the voltage applied to the pin at the top of
the reference resistor chain) should be between +0.1V and
-1.1V. V
RT
should be more positive than V
range. The voltage applied across the reference resistor chain
(V
RT
-V
RB
) must be between 0.8V and 1.2V. The nominal
voltages are V
RT
= 0.00V and V
may be varied dynamically up to 7MHz. Due to slight varia-
tions in the reference current with clock and input signals,
R
T
and R
B
should be low-impedance points. For circuits in
which the reference is not varied, a bypass capacitor to
ground is recommended. If the reference inputs are varied
dynamically as in an Automatic Gain Control (AGC) circuit,
a low-impedance reference source is recommended.
RB
(the voltage
RB
within that
RB
= -1.00V. These voltages
Controls
Two function control pins, NMINV and NLINV are pro-
vided. These controls are for DC (i.e., steady state) use.
They permit the output coding to be either straight binary or
offset two’s complement, in either true or inverted sense,
according to the Output Coding Table.
Convert
The TDC1147 uses a CONVert (CONV) input signal to
initiate the A/D conversion process. Unlike other flash A/D
converters which have a one-clock-cycle pipeline delay
between sampling and output data, the TDC1147 requires
only a single pulse to perform the entire conversion opera-
tion. The analog input is sampled (comparators are latched)
within the maximum Sampling Time Offset (t
Figure 1). Data from that sample becomes valid after a maxi-
mum Output Delay Time (t
D
) while data from the previous
sample is held at the outputs for a minimum Output Hold
Time (t
HO
). This allows data from the TDC1147 to be
acquired by an external register or other circuitry. Note that
there are minimum time requirements for the HIGH and
LOW portions (t
PWH
, t
PWL
) of the CONV waveform and all
output timing specifications are measured with respect to the
rising edge of CONV.
STO
, see
Analog Input
The TDC1147 uses latching comparators which cause the
input impedance to vary slightly with the signal level. For
optimal performance, both V
IN
source impedance of the driving circuit must be less than 30
Ohms. The input signal will not damage the TDC1147 if it
remains within the range of V
EE
is between the V
RT
and V
RB
references, the output will be a
binary number between 0 and 127 inclusive. A signal outside
this range will indicate either full-scale positive or full-scale
negative, depending on whether the signal is off-scale in the
positive or negative direction.
pins must be used and the
to +0.5V. If the input signal
Outputs
The outputs of the TDC1147 are TTL compatible, and capa-
ble of driving four low-power Schottky TTL (54/74 LS) unit
loads. The outputs hold the previous data a minimum time
(t
HO
) after the rising edge of the CONV signal. New data
becomes valid after a maximum time (t
edge of the CONV signal. The use of 2.2 K
tors is recommended.
D
) after the rising
W
pull-up resis-
Pin Assignments
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