參數(shù)資料
型號: TDC1035
廠商: Fairchild Semiconductor Corporation
英文描述: 8-Bit, 30ns Full Response Peak Width Monolithic Peak Digitizer(A/DConverter)(8位, 30ns全響應(yīng)峰值的A/D轉(zhuǎn)換器)
中文描述: 8位,30ns的全面回應(yīng)峰寬峰單片數(shù)字化儀(甲/ DConverter)(8位,30ns的全響應(yīng)峰值的的A / D轉(zhuǎn)換器)
文件頁數(shù): 3/12頁
文件大小: 82K
代理商: TDC1035
PRODUCT SPECIFICATION
TDC1035
3
Command
Two pins, RESET and CLK, control the TDC1035. When
brought HIGH, the level-sensitive RESET control resets the
peak-storing latches. The edge-sensitive CLK control causes
the peak value to be loaded into the output register when a
rising-edge (LOW-to-HIGH) signal is applied. As noted
above, there is a data ambiguity period associated with the
operation of each of these inputs.
Analog Input
Although the TDC1035’s 255 comparators have emitter-
follower isolated inputs, the input impedance can vary up to
25 percent with the signal level, as comparator input transis-
tors switch on or off. As a result, for optimal performance,
the source impedance of the driving device must be less than
25 Ohms. The input signal will not damage the TDC1035 if
it remains in the range V
EE
–0.5V to V
AGND
+0.5V. If the
input signal stays between the V
voltages, the 8-bit digital equivalent of the most negative
voltage reached will be latched into the array of latches,
subject to the dynamic effects mentioned above. A transient
more negative than V
RB
will cause a full-scale output t
after the CLK line rises.
RT
and V
RB
reference
DO
Outputs
The outputs of the TDC1035 are TTL compatible, capable of
driving four low-power Schottky TTL (54LS/74LS) unit
loads or the equivalent. The outputs hold the previous data a
minimum time t
HO
after the rising edge of the CLK input,
and are guaranteed to have the new output value after a
maximum time t
DO
. Under light DC load conditions (such
as driving CMOS loads or base-input low-power Schottky
such as the 74L5374) 2.2k pull-up resistors to +5.0V are
recommended.
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
D
1
(MSB)
D
2
D
3
D
4
D
GND
V
EE
CLK
V
CC
V
EE
D
GND
LINV
D
5
MINV
OE
R
B
A
GND
RMID
V
IN
A
GND
R
T
RESET
D
8
(LSB)
D
7
D
6
65-1035-02
24 Lead Ceramic DIP
18
17
16
15
14
13
12
26
27
28
1
2
3
4
RESET
D
8
D
7
D
6
D
5
LINV
D
GND
R
B
OE
MINV
D
1
(MSB)
D
2
D
3
D
4
2
2
2
2
2
2
1
A
G
R
M
N
N
V
I
A
G
R
T
5
6
7
8
9
1
1
D
G
N
V
E
C
V
C
N
V
E
65-1035-03
28 Lead PLCC
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