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參數(shù)資料
| 型號(hào)： | TDC1035 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 8-Bit, 30ns Full Response Peak Width Monolithic Peak Digitizer（A/DConverter）(8位, 30ns全響應(yīng)峰值的A/D轉(zhuǎn)換器) |
| 中文描述： | 8位，30ns的全面回應(yīng)峰寬峰單片數(shù)字化儀（甲/ DConverter）（8位，30ns的全響應(yīng)峰值的的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大小： | 82K |
| 代理商： | TDC1035 |
TDC1035
PRODUCT SPECIFICATION
2
Functional Description
General Information
The TDC1035 peak detector operates on ground-referenced
negative-going signals. Within t
rising edge of the clock signal CLK, it outputs the most
negative value reached since the previous RESET pulse.
The active-HIGH RESET control is independent of CLK,
but may be connected to CLK to provide a single-control
peak detector. Multiple output cycles are permitted between
reset operations.
RP
nanoseconds after the
The TDC1035 contains parallel array of comparators, an
array of latches, and an encoder which outputs the location
of the highest-valued latch which is set. The TDC1035’s
response characteristics are determined by its comparator
array. A comparator’s response time is determined by the
degree of overdrive, since the output changes only when the
area above threshold reaches a characteristic value. There-
fore, the digitization accuracy of a pulse’s peak value
depends on the shape of the pulse.
To permit accurate, repeatable characterization, the
TDC1035 is tested with a slew-rate limited “square” pulse.
It will digitize (to its DC accuracy) the peak value of a
square pulse having a minimum duration of 30ns. The
accuracy degrades gracefully as the duration decreases from
30 down to 12ns, where it understates the applied amplitude
by 15% (see Figure 5). Production characterization of the
TDC1035 uses “square” pulses with controlled rise and
fall times of 8ns.
Performance of the TDC1035 with other pulse shapes (such
as Gaussian or bandwidth-limited square pulse) can be
estimated by applying an energy above threshold model,
with area of 120 picoVolt-seconds.
The operation of all asynchronous sequential logic circuits
involves some temporal ambiguity. The most common form
of this ambiguity, metastability, occurs in data synchronizers.
In a peak digitizer such as the TDC1035, this ambiguity
comes in the form of periods during which the accuracy of
the measurement of a pulse may be affected, or the pulse
may not even be detected. There is a 10ns (t
period after the falling edge of the RESET signal, during
which detection or accuracy of detection of any pulse is not
guaranteed. There is also a region of 40ns (t
rising edge of the (output) clock (CLK) where a pulse may
be missed or detected inaccurately. These regions are shown
in the timing diagrams, Figure 1 and Figure 2. During the
latter period, if the input signal increases to a new peak
larger than the previously latched value, the value loaded
into the output register may be incorrect (and will most
likely be zero); nonetheless, the peak detection latches will
hold the (correct) new peak value.
RP
) ambiguity
PC
) before the
As shown in Figure 3, the TDC1035’s comparator inputs
have emitter-follower buffers, which limit the permissible
input signal slew rate to 250V/
full-scale transition time of 8ns.
m
s. This corresponds to a
Power
The TDC1035 operates from two supply voltages: +5.0V
and -5.2V. The current return for the positive supply is
D
GND
, and the return for the negative (analog) supply is
A
GND
. All power and ground pins MUST be connected.
Reference
The reference for the TDC1035 is a negative voltage applied
across a chain of 255 resistors. The top of this chain is
connected to the R
T
pin, and the voltage applied to the R
pin (V
RT
) should be within 0.1V of the analog ground. Note
that the difference between the voltage applied to the pin and
the voltage at the reference chain is the offset specification
(E
OT
and E
OB
). The bottom of the reference resistor chain is
connected to the R
B
pin, and the voltage applied to the R
pin (V
RB
) should be between 1.8 and 2.2V negative with
respect to the R
T
pin for full-specification operation.
Reduced reference voltage operation is possible at reduced
accuracy (for example, for generating a nonlinear transfer
function). The R
T
–R
B
reference source should be able to
deliver at least 45mA.
T
B
Due to the variation in the reference currents with clock and
input signals, R
T
and R
B
should be connected to circuit
nodes with a low impedance to ground. For circuits in which
the reference is not varied at a high rate, a bypass capacitor
to ground is recommended. If the reference inputs are
exercised dynamically (e.g., for AGC or nonlinear opera-
tion), a low-impedance reference source is required. The ref-
erence voltages may be varied dynamically; contact the
factory for information on limitations when the device is
used in this mode. The performance of the TDC1035 is spec-
ified with DC references of V
RT
= 0.0V and V
RB
= -2.0V.
Control
Two function control pins, MINV and LINV, are provided.
These names stand for active-LOW Most significant bit
INVert and active-LOW Least significant bits INVert,
respectively These controls are for DC (i.e., steadystate), not
dynamic, use. They permit the output coding to be either
straight binary or offset two’s complement, in either true
or inverted sense, according to the Output Coding Table.
A single output state control pin, OE, is provided. The
three-state outputs may be placed in a high-impedance state
by applying a logic HIGH to the OE control pin, and enabled
by driving OE LOW.
The function control pins may be tied to V
HIGH, and D
GND
for a logic LOW; however, a 2.2 kOhm
pull-up resistor is preferred over direct connection to V
If a pull-up resistor is not used, the absolute maximum volt-
age rating for the part becomes that of the TTL input, 5.5V,
rather than the higher value for the V
CC
for a logic
CC
.
CC
terminal.
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